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Revision 1.34 / (download) - annotate - [select for diffs], Sat Feb 25 00:40:22 2023 UTC (3 months, 1 week ago) by riastradh
Branch: MAIN
CVS Tags: HEAD
Changes since 1.33: +8 -2
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Diff to previous 1.33 (colored)
aarch64: curcpu() audit. Sprinkle KASSERT (or KDASSERT in hot paths) for kpreempt_disabled() when we use curcpu() and it's not immediately obvious that the caller has preemption disabled but closer scrutiny suggests the caller has. Note unsafe curcpu()s for syscall event counting. Not sure this is worth changing. Possible bugs fixed: - cpu_irq and cpu_fiq could be preempted while trying to run softints on this CPU. - data_abort_handler might incorrectly think it was invoked in interrupt context when it was only preempted and migrated to another CPU. - pmap_fault_fixup might report the wrong CPU logs. (However, we don't currently run with kpreemption on aarch64, so these are not yet real bugs fixed except if you patch it to build with __HAVE_PREEMPTION.)
Revision 1.33 / (download) - annotate - [select for diffs], Mon Jan 31 09:16:09 2022 UTC (16 months ago) by ryo
Branch: MAIN
CVS Tags: netbsd-10-base,
netbsd-10,
bouyer-sunxi-drm-base,
bouyer-sunxi-drm
Changes since 1.32: +68 -2
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Diff to previous 1.32 (colored)
add support Hardware updates to Access flag and Dirty state (FEAT_HAFDBS)
- The DBM bit of the PTE is now used to determine if it is writable, and
the AF bit is treated entirely as a reference bit. A valid PTE is always
treated as readable. There can be no valid PTE that is not readable.
- LX_BLKPAG_OS_{READ,WRITE} are used only for debugging purposes,
and has been superseded by LX_BLKPAG_AF and LX_BLKPAG_DBM.
- Improve comment
The need for reference/modify emulation has been eliminated,
and access/permission faults have been reduced, however,
there has been little change in overall performance.
Revision 1.32 / (download) - annotate - [select for diffs], Sun Oct 31 16:23:47 2021 UTC (19 months ago) by skrll
Branch: MAIN
Changes since 1.31: +42 -51
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Diff to previous 1.31 (colored)
Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep. The AP initialisation code in cpu_init_secondary_processor will read and initialise the required system registers and state for the BP to attach and report. Rework the interrupt handler code for this new sequence. Thankfully, this removes a bunch of code for bcm2836mp. The VFP detection handler on <= armv7 relies on the global undefined handler being in place until the BP attaches vfp. That is, after the APs have been spun up. gicv3_its.c has a serialisation issue which is protected against in the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin lock. The serialisation issue needs addressing more completely. Tested on RPI3, Apple M1, QEMU, and lx2k Fixes PR port-arm/56264: diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3
Revision 1.31 / (download) - annotate - [select for diffs], Sun Oct 31 07:56:55 2021 UTC (19 months ago) by skrll
Branch: MAIN
Changes since 1.30: +10 -14
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Diff to previous 1.30 (colored)
Sprinkle some const
Revision 1.30 / (download) - annotate - [select for diffs], Sat Oct 23 06:48:31 2021 UTC (19 months, 1 week ago) by skrll
Branch: MAIN
Changes since 1.29: +3 -3
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Diff to previous 1.29 (colored)
Shrink a panic message to avoid a long line
Revision 1.29 / (download) - annotate - [select for diffs], Sat Oct 23 05:42:49 2021 UTC (19 months, 1 week ago) by skrll
Branch: MAIN
Changes since 1.28: +6 -6
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Diff to previous 1.28 (colored)
Remove unnecessary brackets in a conditional
Revision 1.28 / (download) - annotate - [select for diffs], Thu Sep 23 06:34:00 2021 UTC (20 months, 1 week ago) by skrll
Branch: MAIN
Changes since 1.27: +4 -4
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Diff to previous 1.27 (colored)
Print the cache information in similar formats and arm and aarch64, e.g. arm before [ 1.0000000] cpu0: 32KB/64B 2-way L1 PIPT Instruction cache [ 1.0000000] cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache [ 1.0000000] cpu0: 2304KB/64B 16-way write-through L2 PIPT Unified cache arm after [ 1.0000000] cpu0: L1 32KB/64B 2-way (256 set) PIPT Instruction cache [ 1.0000000] cpu0: L1 32KB/64B 2-way (256 set) write-back-locking-C PIPT Data cache [ 1.0000000] cpu0: L2 2304KB/64B 16-way (2304 set) write-through PIPT Unified cache aarch64 before [ 1.0000030] cpu1: L1 48KB/64B*256L*3W PIPT Instruction cache [ 1.0000030] cpu1: L1 32KB/64B*256L*2W PIPT Data cache [ 1.0000030] cpu1: L2 2048KB/64B*2048L*16W PIPT Unified cache aarch64 after [ 1.0000030] cpu1: L1 48KB/64B 3-way (256 set) PIPT Instruction cache [ 1.0000030] cpu1: L1 32KB/64B 2-way (256 set) PIPT Data cache [ 1.0000030] cpu1: L2 2048KB/64B 16-way (2048 set) PIPT Unified cache
Revision 1.26.2.1 / (download) - annotate - [select for diffs], Sat Apr 3 22:28:13 2021 UTC (2 years, 2 months ago) by thorpej
Branch: thorpej-futex
Changes since 1.26: +4 -3
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Diff to previous 1.26 (colored) next main 1.27 (colored)
Sync with HEAD.
Revision 1.27 / (download) - annotate - [select for diffs], Mon Jan 11 17:12:13 2021 UTC (2 years, 4 months ago) by skrll
Branch: MAIN
CVS Tags: thorpej-i2c-spi-conf2-base,
thorpej-i2c-spi-conf2,
thorpej-i2c-spi-conf-base,
thorpej-i2c-spi-conf,
thorpej-futex2-base,
thorpej-futex2,
thorpej-futex-base,
thorpej-cfargs2-base,
thorpej-cfargs2,
thorpej-cfargs-base,
thorpej-cfargs,
cjep_sun2x-base1,
cjep_sun2x-base,
cjep_sun2x,
cjep_staticlib_x-base1,
cjep_staticlib_x-base,
cjep_staticlib_x
Changes since 1.26: +4 -3
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Diff to previous 1.26 (colored)
Small simplification
Revision 1.5.4.2 / (download) - annotate - [select for diffs], Fri Jan 1 12:38:49 2021 UTC (2 years, 5 months ago) by martin
Branch: netbsd-9
CVS Tags: netbsd-9-3-RELEASE,
netbsd-9-2-RELEASE
Changes since 1.5.4.1: +16 -6
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Diff to previous 1.5.4.1 (colored) to branchpoint 1.5 (colored) next main 1.6 (colored)
Pull up following revision(s) (requested by rin in ticket #1170): sys/arch/aarch64/aarch64/cpufunc.c: revision 1.22 (patch) sys/arch/aarch64/aarch64/cpufunc.c: revision 1.23 (patch) sys/arch/aarch64/aarch64/pmap.c: revision 1.81 Set uvmexp.ncolors appropriately, which is required for some CPU models with VIPT icache. Otherwise, alias in virtual address results in inconsistent results, at least for applications that rewrite text of other process, e.g., GDB for arm32. Also, this hopefully fixes other unexpected failures due to alias. Confirmed that there's no observable regression in performance; difference in ``time make -j8'' for GENERIC64 kernel on BCM2837 with and without setting uvmexp.ncolors is within 0.1%. Thanks to ryo@ for discussion. Fix uvmexp.ncolors for some big.LITTLE configuration; it is uncertain which CPU is used as primary, and as a result, secondary CPUs can require larger number of colors. In order to solve this problem, update uvmexp.ncolors via uvm_page_recolor(9) when secondary CPUs are attached, as done for other ports like x86. Pointed out by jmcneill@, and discussed on port-arm@: http://mail-index.netbsd.org/port-arm/2020/07/03/msg006837.html Tested and OK'd by ryo@. Fix previous; add missing <uvm/uvm.h> include.
Revision 1.26 / (download) - annotate - [select for diffs], Thu Oct 22 07:31:15 2020 UTC (2 years, 7 months ago) by skrll
Branch: MAIN
Branch point for: thorpej-futex
Changes since 1.25: +9 -9
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Diff to previous 1.25 (colored)
Use the dmb/dsb/isb macros... if nothing else they're all now consistent about the "memory" assembler contraint. No binary change
Revision 1.25 / (download) - annotate - [select for diffs], Thu Oct 22 07:23:24 2020 UTC (2 years, 7 months ago) by skrll
Branch: MAIN
Changes since 1.24: +3 -3
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Diff to previous 1.24 (colored)
Simplify the cpufunc.h header, i.e. always use #include <arm/cpufunc.h>
Revision 1.24 / (download) - annotate - [select for diffs], Sun Aug 2 06:58:16 2020 UTC (2 years, 10 months ago) by maxv
Branch: MAIN
Changes since 1.23: +33 -2
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Diff to previous 1.23 (colored)
Add support for Privileged Access Never (ARMv8.1-PAN). PAN provides the same functionality as SMAP on x86: it forbids kernel access to userland pages when PSTATE.PAN=1, and allows such accesses when PSTATE.PAN=0. We clear SCTLR_SPAN, to guarantee that PAN=1 each time the kernel is entered. We catch PAN faults and panic right away without further processing. In copyin, copyout, etc, we temporarily authorize access to userland pages. PAN is a very useful exploit mitigation. Reviewed by ryo@, thanks. Tested on Qemu. Enabled by default.
Revision 1.23 / (download) - annotate - [select for diffs], Sat Jul 4 04:59:36 2020 UTC (2 years, 11 months ago) by rin
Branch: MAIN
Changes since 1.22: +3 -2
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Diff to previous 1.22 (colored)
Fix previous; add missing <uvm/uvm.h> include.
Revision 1.22 / (download) - annotate - [select for diffs], Sat Jul 4 04:39:20 2020 UTC (2 years, 11 months ago) by rin
Branch: MAIN
Changes since 1.21: +15 -6
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Diff to previous 1.21 (colored)
Fix uvmexp.ncolors for some big.LITTLE configuration; it is uncertain which CPU is used as primary, and as a result, secondary CPUs can require larger number of colors. In order to solve this problem, update uvmexp.ncolors via uvm_page_recolor(9) when secondary CPUs are attached, as done for other ports like x86. Pointed out by jmcneill@, and discussed on port-arm@: http://mail-index.netbsd.org/port-arm/2020/07/03/msg006837.html Tested and OK'd by ryo@.
Revision 1.21 / (download) - annotate - [select for diffs], Wed Jul 1 07:59:16 2020 UTC (2 years, 11 months ago) by ryo
Branch: MAIN
Changes since 1.20: +21 -3
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Diff to previous 1.20 (colored)
Switch the Icache sync operation to the necessary and sufficient one according to the CTR_EL0.DIC and CTR_EL0.IDC flags. If CTR_EL0.DIC=1, Icache invalidation is not required. If CTR_EL0.IDC=1, Dcache clean before Icache invalidation is not required. CLIDR_EL1.LoC is 0, or CLIDR_EL1.LoUIS and CLIDR_EL1.LoUU are 0, Dcache clean is not required as well. SEE ALSO ARMARM, "CTR_EL0 Cache Type Register", and "CLIDR_EL1 Cache Level ID Register"
Revision 1.20 / (download) - annotate - [select for diffs], Mon May 25 05:13:16 2020 UTC (3 years ago) by ryo
Branch: MAIN
Changes since 1.19: +26 -22
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Diff to previous 1.19 (colored)
cache information can be detected correctly on newer CPUs - add VPIPT cache type - adapt to 64-bit CCSIDR (ARMv8.3-CCIDX) - CCSIDR:[WT,WB,PA,WA] are deprecated - show number of cache lines when attaching cpu
Revision 1.19 / (download) - annotate - [select for diffs], Sat May 23 18:08:58 2020 UTC (3 years ago) by ryo
Branch: MAIN
Changes since 1.18: +4 -4
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Diff to previous 1.18 (colored)
Not only the kernel thread, but also the userland PAC keys (APIA,APIB,APDA,APDB,APGA) are now randomly initialized at exec, and switched when context switch. userland programs are able to perform pointer authentication on ARMv8.3+PAC cpu. reviewd by maxv@, thanks.
Revision 1.18 / (download) - annotate - [select for diffs], Fri May 15 04:55:40 2020 UTC (3 years ago) by ryo
Branch: MAIN
Changes since 1.17: +12 -12
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Diff to previous 1.17 (colored)
SCTLR_EnIA should be enabled in the caller(locore). For some reason, gcc make aarch64_pac_init() function non-leaf, and it uses paciasp/autiasp.
Revision 1.1.4.3 / (download) - annotate - [select for diffs], Tue Apr 21 18:42:02 2020 UTC (3 years, 1 month ago) by martin
Branch: phil-wifi
Changes since 1.1.4.2: +44 -0
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Diff to previous 1.1.4.2 (colored) to branchpoint 1.1 (colored) next main 1.2 (colored)
Sync with HEAD
Revision 1.16.2.1 / (download) - annotate - [select for diffs], Mon Apr 20 11:28:50 2020 UTC (3 years, 1 month ago) by bouyer
Branch: bouyer-xenpvh
Changes since 1.16: +46 -2
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Diff to previous 1.16 (colored) next main 1.17 (colored)
Sync with HEAD
Revision 1.1.4.2 / (download) - annotate - [select for diffs], Mon Apr 13 08:03:27 2020 UTC (3 years, 1 month ago) by martin
Branch: phil-wifi
Changes since 1.1.4.1: +26 -16
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Diff to previous 1.1.4.1 (colored) to branchpoint 1.1 (colored)
Mostly merge changes from HEAD upto 20200411
Revision 1.17 / (download) - annotate - [select for diffs], Sun Apr 12 07:49:58 2020 UTC (3 years, 1 month ago) by maxv
Branch: MAIN
CVS Tags: phil-wifi-20200421,
bouyer-xenpvh-base2,
bouyer-xenpvh-base1
Changes since 1.16: +46 -2
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Diff to previous 1.16 (colored)
Add support for Pointer Authentication (PAC). We use the "pac-ret" option, to sign the return instruction pointer on function entry, and authenticate it on function exit. This acts as a mitigation against ROP. The authentication uses a per-lwp (secret) I-A key stored in the 128bit APIAKey register and part of the lwp context. During lwp creation, the kernel generates a random key, and during context switches, it installs the key of the target lwp on the CPU. Userland cannot read the APIAKey register directly. However, it can sign its pointers with it, because the register is architecturally shared between userland and the kernel. Although part of the CPU design, it is a bit of an undesired behavior, because it allows to forge valid kernel pointers from userland. To avoid that, we don't share the key with userland, and rather switch it in EL0<->EL1 transitions. This means that when userland executes, a different key is loaded in APIAKey than the one the kernel uses. For now the userland key is a fixed 128bit zero value. The DDB stack unwinder is changed to strip the authentication code from the pointers in lr. Two problems are known: * Currently the idlelwps' keys are not really secret. This is because the RNG is not yet available when we spawn these lwps. Not overly important, but would be nice to fix with UEFI RNG. * The key switching in EL0<->EL1 transitions is not the most optimized code on the planet. Instead of checking aarch64_pac_enabled, it would be better to hot-patch the code at boot time, but there currently is no hot-patch support on aarch64. Tested on Qemu.
Revision 1.16 / (download) - annotate - [select for diffs], Sun Apr 5 22:54:51 2020 UTC (3 years, 1 month ago) by jmcneill
Branch: MAIN
CVS Tags: phil-wifi-20200411,
phil-wifi-20200406,
bouyer-xenpvh-base
Branch point for: bouyer-xenpvh
Changes since 1.15: +3 -3
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Diff to previous 1.15 (colored)
Cleanup CPU attach output: - Always print the core's vendor and product name. - Print the CPU ID on the same line as the name. Single line of dmesg per core. - Use aprint_verbose for reporting additional details.
Revision 1.12.2.1 / (download) - annotate - [select for diffs], Fri Jan 17 21:47:22 2020 UTC (3 years, 4 months ago) by ad
Branch: ad-namecache
Changes since 1.12: +2 -21
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Diff to previous 1.12 (colored) next main 1.13 (colored)
Sync with head.
Revision 1.15 / (download) - annotate - [select for diffs], Wed Jan 15 08:34:04 2020 UTC (3 years, 4 months ago) by mrg
Branch: MAIN
CVS Tags: is-mlppp-base,
is-mlppp,
ad-namecache-base3,
ad-namecache-base2,
ad-namecache-base1
Changes since 1.14: +2 -23
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Diff to previous 1.14 (colored)
port the arm64 cpu topology setup for big.little to arm. rename arm64 cpu_do_topology() to arm_cpu_do_topology() and call it from both arm cpu_attach(). replace both aarch64_set_topology() inline code in arm cpu_attach() with new arm_cpu_do_topology(), which is called by the arm64 locore as well (possibly not needed, which would allow it to become static.) not yet tested on a real big.little armv7 system. tested on rockpro64 and pinebook pro.
Revision 1.14 / (download) - annotate - [select for diffs], Sun Jan 12 09:29:18 2020 UTC (3 years, 4 months ago) by mrg
Branch: MAIN
Changes since 1.13: +5 -5
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Diff to previous 1.13 (colored)
provide some semblance of valid cpu topology for big.little systems. while attaching cpus, if the FDT provides "capacity-dmips-mhz" track the fastest set, and call cpu_topology_set() with slow=true for any cpus that are not the fastest. bug fix for cpu_topology_set(): actually set ci_is_slow for slow cpus. with this change, and -current's recent scheduler changes, this means that long running processes run on the faster cores. on RK3399 based systems, i am seeing 20-50% speed ups for many tasks. XXX: all this can be made common with armv7 big.little.
Revision 1.13 / (download) - annotate - [select for diffs], Thu Jan 9 16:35:03 2020 UTC (3 years, 4 months ago) by ad
Branch: MAIN
Changes since 1.12: +6 -4
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Diff to previous 1.12 (colored)
- Many small tweaks to the SMT awareness in the scheduler. It does a much better job now at keeping all physical CPUs busy, while using the extra threads to help out. In particular, during preempt() if we're using SMT, try to find a better CPU to run on and teleport curlwp there. - Change the CPU topology stuff so it can work on asymmetric systems. This mainly entails rearranging one of the CPU lists so it makes sense in all configurations. - Add a parameter to cpu_topology_set() to note that a CPU is "slow", for where there are fast CPUs and slow CPUs, like with the Rockwell RK3399. Extend the SMT awareness to try and handle that situation too (keep fast CPUs busy, use slow CPUs as helpers).
Revision 1.12 / (download) - annotate - [select for diffs], Fri Dec 20 21:05:33 2019 UTC (3 years, 5 months ago) by ad
Branch: MAIN
CVS Tags: ad-namecache-base
Branch point for: ad-namecache
Changes since 1.11: +5 -3
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Diff to previous 1.11 (colored)
Some more CPU topology stuff: - Use cegger@'s ACPI SRAT parsing code to figure out NUMA node ID for each CPU as it is attached. - For scheduler experiments with SMT, flag CPUs with the lowest numbered SMT IDs as "primaries", link back to the primaries from secondaries, and build a circular list of CPUs in each package with identical SMT IDs. - No need for package/core/smt/numa IDs to be anything other than a u_int.
Revision 1.11 / (download) - annotate - [select for diffs], Thu Dec 5 05:45:52 2019 UTC (3 years, 6 months ago) by ryo
Branch: MAIN
Changes since 1.10: +3 -3
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Diff to previous 1.10 (colored)
fix build error by my previous commit
Revision 1.10 / (download) - annotate - [select for diffs], Thu Dec 5 05:17:55 2019 UTC (3 years, 6 months ago) by ryo
Branch: MAIN
Changes since 1.9: +3 -3
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Diff to previous 1.9 (colored)
MAX_CACHE_LEVEL * struct aarch64_cache_info are required to statically allocate for cpu0. avoid "cpu0: L2 512KB/64B 16-way write-back read-allocate write-allocate PIPT *UNK* cache" by r1.8
Revision 1.9 / (download) - annotate - [select for diffs], Mon Dec 2 23:22:43 2019 UTC (3 years, 6 months ago) by ad
Branch: MAIN
Changes since 1.8: +11 -8
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Diff to previous 1.8 (colored)
Take the basic CPU topology information we already collect, and use it to make circular lists of CPU siblings in the same core, and in the same package. Nothing fancy, just enough to have a bit of fun in the scheduler trying out different tactics.
Revision 1.8 / (download) - annotate - [select for diffs], Fri Nov 22 05:21:19 2019 UTC (3 years, 6 months ago) by mlelstv
Branch: MAIN
Changes since 1.7: +31 -11
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Diff to previous 1.7 (colored)
Make cache operations available early.
Revision 1.7 / (download) - annotate - [select for diffs], Tue Oct 1 18:00:07 2019 UTC (3 years, 8 months ago) by chs
Branch: MAIN
CVS Tags: phil-wifi-20191119
Changes since 1.6: +3 -4
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Diff to previous 1.6 (colored)
in many device attach paths, allocate memory with KM_SLEEP instead of KM_NOSLEEP and remove code to handle failures that can no longer happen.
Revision 1.5.4.1 / (download) - annotate - [select for diffs], Sun Sep 22 12:27:22 2019 UTC (3 years, 8 months ago) by martin
Branch: netbsd-9
CVS Tags: netbsd-9-1-RELEASE,
netbsd-9-0-RELEASE,
netbsd-9-0-RC2,
netbsd-9-0-RC1
Changes since 1.5: +9 -4
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Diff to previous 1.5 (colored)
Pull up following revision(s) (requested by jmcneill in ticket #221): sys/arch/aarch64/aarch64/cpufunc.c: revision 1.6 Do not attempt to change coherency_unit at runtime. Instead, if the required coherency unit is greater than COHERENCY_UNIT in a MULTIPROCESSOR kernel, just panic instead. This makes non-MULTIPROCESSOR kernels work again.
Revision 1.6 / (download) - annotate - [select for diffs], Thu Sep 12 09:05:28 2019 UTC (3 years, 8 months ago) by jmcneill
Branch: MAIN
Changes since 1.5: +9 -4
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Diff to previous 1.5 (colored)
Do not attempt to change coherency_unit at runtime. Instead, if the required coherency unit is greater than COHERENCY_UNIT in a MULTIPROCESSOR kernel, just panic instead. This makes non-MULTIPROCESSOR kernels work again.
Revision 1.1.4.1 / (download) - annotate - [select for diffs], Mon Jun 10 22:05:42 2019 UTC (3 years, 11 months ago) by christos
Branch: phil-wifi
Changes since 1.1: +188 -37
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Diff to previous 1.1 (colored)
Sync with HEAD
Revision 1.1.2.5 / (download) - annotate - [select for diffs], Wed Dec 26 14:01:30 2018 UTC (4 years, 5 months ago) by pgoyette
Branch: pgoyette-compat
CVS Tags: pgoyette-compat-merge-20190127
Changes since 1.1.2.4: +26 -2
lines
Diff to previous 1.1.2.4 (colored) to branchpoint 1.1 (colored) next main 1.2 (colored)
Sync with HEAD, resolve a few conflicts
Revision 1.5 / (download) - annotate - [select for diffs], Fri Dec 21 08:01:01 2018 UTC (4 years, 5 months ago) by ryo
Branch: MAIN
CVS Tags: phil-wifi-20190609,
pgoyette-compat-20190127,
pgoyette-compat-20190118,
pgoyette-compat-1226,
netbsd-9-base,
isaki-audio2-base,
isaki-audio2
Branch point for: netbsd-9
Changes since 1.4: +26 -2
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Diff to previous 1.4 (colored)
- add workaround for Cavium ThunderX errata 27456. - add cpufuncs table in cpu_info. each cpu clusters may have different erratum. (e.g. big.LITTLE)
Revision 1.1.2.4 / (download) - annotate - [select for diffs], Thu Sep 6 06:55:22 2018 UTC (4 years, 8 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1.2.3: +161 -37
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Diff to previous 1.1.2.3 (colored) to branchpoint 1.1 (colored)
Sync with HEAD Resolve a couple of conflicts (result of the uimin/uimax changes)
Revision 1.4 / (download) - annotate - [select for diffs], Wed Aug 29 06:16:40 2018 UTC (4 years, 9 months ago) by ryo
Branch: MAIN
CVS Tags: pgoyette-compat-1126,
pgoyette-compat-1020,
pgoyette-compat-0930,
pgoyette-compat-0906
Changes since 1.3: +5 -2
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Diff to previous 1.3 (colored)
Update coherency_unit if needed. Pointed out by skrll@
Revision 1.3 / (download) - annotate - [select for diffs], Sun Aug 26 18:15:49 2018 UTC (4 years, 9 months ago) by ryo
Branch: MAIN
Changes since 1.2: +158 -37
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Diff to previous 1.2 (colored)
add support multiple cpu clusters. * pass cpu index as an argument to secondary processors when hatching. * keep cpu cache confituration per cpu clusters. Hello big.LITTLE!
Revision 1.1.2.3 / (download) - annotate - [select for diffs], Sat Jul 28 04:37:25 2018 UTC (4 years, 10 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1.2.2: +5 -2
lines
Diff to previous 1.1.2.2 (colored) to branchpoint 1.1 (colored)
Sync with HEAD
Revision 1.2 / (download) - annotate - [select for diffs], Tue Jul 17 00:30:34 2018 UTC (4 years, 10 months ago) by christos
Branch: MAIN
CVS Tags: pgoyette-compat-0728
Changes since 1.1: +5 -2
lines
Diff to previous 1.1 (colored)
add default statement
Revision 1.1.2.2 / (download) - annotate - [select for diffs], Sat Apr 7 04:12:10 2018 UTC (5 years, 1 month ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1.2.1: +279 -0
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Diff to previous 1.1.2.1 (colored) to branchpoint 1.1 (colored)
Sync with HEAD. 77 conflicts resolved - all of them $NetBSD$
Revision 1.1.2.1, Sun Apr 1 04:35:03 2018 UTC (5 years, 2 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1: +0 -279
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FILE REMOVED
file cpufunc.c was added on branch pgoyette-compat on 2018-04-07 04:12:10 +0000
Revision 1.1 / (download) - annotate - [select for diffs], Sun Apr 1 04:35:03 2018 UTC (5 years, 2 months ago) by ryo
Branch: MAIN
CVS Tags: phil-wifi-base,
pgoyette-compat-0625,
pgoyette-compat-0521,
pgoyette-compat-0502,
pgoyette-compat-0422,
pgoyette-compat-0415,
pgoyette-compat-0407
Branch point for: phil-wifi,
pgoyette-compat
Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@) - sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@) - add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)