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CVS log for src/sys/arch/aarch64/aarch64/cpu.c

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Request diff between arbitrary revisions


Default branch: MAIN


Revision 1.73 / (download) - annotate - [select for diffs], Fri Feb 3 08:05:27 2023 UTC (2 days, 16 hours ago) by skrll
Branch: MAIN
CVS Tags: HEAD
Changes since 1.72: +4 -4 lines
Diff to previous 1.72 (colored)

Remove useless/harmful casts in debug messages. MPIDR AFF3 would not
be printed before.

Revision 1.70.4.1 / (download) - annotate - [select for diffs], Fri Dec 23 08:09:48 2022 UTC (6 weeks, 2 days ago) by martin
Branch: netbsd-10
Changes since 1.70: +4 -3 lines
Diff to previous 1.70 (colored) next main 1.71 (colored)

Pull up following revision(s) (requested by ryo in ticket #20):

	sys/arch/arm/arm/cpufunc.c: revision 1.185
	sys/dev/tprof/tprof.c: revision 1.22
	sys/arch/arm/arm32/arm32_boot.c: revision 1.45
	sys/dev/tprof/tprof_armv8.c: revision 1.19
	sys/dev/tprof/tprof_armv7.c: revision 1.12
	sys/arch/aarch64/aarch64/cpu.c: revision 1.71
	sys/arch/aarch64/aarch64/cpu.c: revision 1.72

tprof_lock is not a spin mutex. use mutex_{enter,exit}(). oops

Explicitly disable overflow interrupts before enabling the cycle counter.

PMCR_EL0.LC should be set. ARM deprecates use of PMCR_EL0.LC=0

Even if an overflow interrupt is occured for a counter outside tprof management,
the bit of onverflow status register must be cleared to prevent an interrupt storm.

Revision 1.72 / (download) - annotate - [select for diffs], Thu Dec 22 06:58:47 2022 UTC (6 weeks, 3 days ago) by ryo
Branch: MAIN
Changes since 1.71: +3 -3 lines
Diff to previous 1.71 (colored)

PMCR_EL0.LC should be set. ARM deprecates use of PMCR_EL0.LC=0

Revision 1.71 / (download) - annotate - [select for diffs], Thu Dec 22 06:58:07 2022 UTC (6 weeks, 3 days ago) by ryo
Branch: MAIN
Changes since 1.70: +3 -2 lines
Diff to previous 1.70 (colored)

Explicitly disable overflow interrupts before enabling the cycle counter.

Revision 1.70 / (download) - annotate - [select for diffs], Sun May 29 16:14:41 2022 UTC (8 months, 1 week ago) by ryo
Branch: MAIN
CVS Tags: netbsd-10-base, bouyer-sunxi-drm-base, bouyer-sunxi-drm
Branch point for: netbsd-10
Changes since 1.69: +4 -2 lines
Diff to previous 1.69 (colored)

fix build without options DDB

Revision 1.69 / (download) - annotate - [select for diffs], Thu Mar 3 06:26:05 2022 UTC (11 months ago) by riastradh
Branch: MAIN
Changes since 1.68: +4 -4 lines
Diff to previous 1.68 (colored)

arm: Use device_set_private for cpuN.

For cpu at fdt, nix the fdt softc -- this was leaked and never used
for anything.  The device's private storage is the cpu_info.

Revision 1.68 / (download) - annotate - [select for diffs], Fri Nov 12 06:44:46 2021 UTC (14 months, 3 weeks ago) by skrll
Branch: MAIN
Changes since 1.67: +14 -6 lines
Diff to previous 1.67 (colored)

Print a big warning about trying to run on early ThunderX parts

Revision 1.67 / (download) - annotate - [select for diffs], Sun Oct 31 16:23:47 2021 UTC (15 months ago) by skrll
Branch: MAIN
Changes since 1.66: +60 -43 lines
Diff to previous 1.66 (colored)

Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep.

The AP initialisation code in cpu_init_secondary_processor will read and
initialise the required system registers and state for the BP to attach
and report.

Rework the interrupt handler code for this new sequence. Thankfully,
this removes a bunch of code for bcm2836mp.

The VFP detection handler on <= armv7 relies on the global undefined
handler being in place until the BP attaches vfp. That is, after the
APs have been spun up.

gicv3_its.c has a serialisation issue which is protected against in
the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin
lock. The serialisation issue needs addressing more completely.

Tested on RPI3, Apple M1, QEMU, and lx2k

Fixes PR port-arm/56264:
   diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3

Revision 1.66 / (download) - annotate - [select for diffs], Sat Oct 30 10:47:03 2021 UTC (15 months, 1 week ago) by skrll
Branch: MAIN
Changes since 1.65: +2 -5 lines
Diff to previous 1.65 (colored)

G/C MD_CPU_HATCH. It's old evbarm (<= armv7)

Revision 1.65 / (download) - annotate - [select for diffs], Sat Oct 30 09:42:27 2021 UTC (15 months, 1 week ago) by skrll
Branch: MAIN
Changes since 1.64: +3 -3 lines
Diff to previous 1.64 (colored)

style. NFCI.

Revision 1.64 / (download) - annotate - [select for diffs], Sun Oct 17 07:26:20 2021 UTC (15 months, 2 weeks ago) by skrll
Branch: MAIN
Changes since 1.63: +2 -4 lines
Diff to previous 1.63 (colored)

Remove some newlines

Revision 1.63 / (download) - annotate - [select for diffs], Sun Oct 10 07:41:21 2021 UTC (15 months, 3 weeks ago) by skrll
Branch: MAIN
Changes since 1.62: +3 -2 lines
Diff to previous 1.62 (colored)

Need to call pmap_tlb_info_attach for each CPU.  Missed in previous
commit.
CVS ----------------------------------------------------------------------

Revision 1.62 / (download) - annotate - [select for diffs], Mon Oct 4 09:39:18 2021 UTC (16 months ago) by skrll
Branch: MAIN
Changes since 1.61: +3 -2 lines
Diff to previous 1.61 (colored)

Add a KASSERT

Revision 1.61 / (download) - annotate - [select for diffs], Mon Aug 30 22:57:33 2021 UTC (17 months ago) by jmcneill
Branch: MAIN
Changes since 1.60: +4 -2 lines
Diff to previous 1.60 (colored)

Identify Apple M1 "Icestorm" and "Firestorm" CPU types.

Revision 1.59.4.1 / (download) - annotate - [select for diffs], Sun Aug 1 22:41:59 2021 UTC (18 months ago) by thorpej
Branch: thorpej-i2c-spi-conf
Changes since 1.59: +6 -2 lines
Diff to previous 1.59 (colored) next main 1.60 (colored)

Sync with HEAD.

Revision 1.60 / (download) - annotate - [select for diffs], Sat Jun 19 13:40:00 2021 UTC (19 months, 2 weeks ago) by jmcneill
Branch: MAIN
CVS Tags: thorpej-i2c-spi-conf2-base, thorpej-i2c-spi-conf2, thorpej-i2c-spi-conf-base, thorpej-futex2-base, thorpej-futex2, thorpej-cfargs2-base, thorpej-cfargs2
Changes since 1.59: +6 -2 lines
Diff to previous 1.59 (colored)

Do not try to initialize PMU if ID_AA64DFR0_EL1 reports a non-standard
PMU implementation.

Revision 1.56.2.2 / (download) - annotate - [select for diffs], Sat Apr 3 22:28:13 2021 UTC (22 months ago) by thorpej
Branch: thorpej-futex
Changes since 1.56.2.1: +11 -5 lines
Diff to previous 1.56.2.1 (colored) next main 1.57 (colored)

Sync with HEAD.

Revision 1.59 / (download) - annotate - [select for diffs], Tue Mar 9 16:44:27 2021 UTC (22 months, 4 weeks ago) by ryo
Branch: MAIN
CVS Tags: thorpej-futex-base, thorpej-cfargs-base, thorpej-cfargs, cjep_sun2x-base1, cjep_sun2x-base, cjep_sun2x, cjep_staticlib_x-base1, cjep_staticlib_x-base, cjep_staticlib_x
Branch point for: thorpej-i2c-spi-conf
Changes since 1.58: +9 -3 lines
Diff to previous 1.58 (colored)

Add support hardware breakpoint and watchpoint again.

Limited support for hardware watchpoint has been available for some time, but it
has not been working properly. In addition, it stopped working at the time of
the PTRACE support commit on 2018-12-13. This has been fixed to work correctly,
and also fixed to be practical by sharing hardware watchpoints and breakpoints
between CPUs on MULTIPROCESSOR.

Also fixed a bug that causes a malfunction when switching CPUs with
"machine cpu N" when entering ddb mode from other than cpu_Debugger().

I have confirmed that the CPU can be switched by "machine cpu N" and return from
ddb properly in each case where ddb is called triggered by ddb break/watchpoint,
hardware break/watchpoint, and cpu_Debugger().

Revision 1.58 / (download) - annotate - [select for diffs], Mon Jan 11 21:58:31 2021 UTC (2 years ago) by skrll
Branch: MAIN
Changes since 1.57: +4 -4 lines
Diff to previous 1.57 (colored)

Improve a comment

Revision 1.56.2.1 / (download) - annotate - [select for diffs], Mon Dec 14 14:37:44 2020 UTC (2 years, 1 month ago) by thorpej
Branch: thorpej-futex
Changes since 1.56: +3 -3 lines
Diff to previous 1.56 (colored)

Sync w/ HEAD.

Revision 1.57 / (download) - annotate - [select for diffs], Fri Dec 11 18:03:33 2020 UTC (2 years, 1 month ago) by skrll
Branch: MAIN
Changes since 1.56: +3 -3 lines
Diff to previous 1.56 (colored)

s:aarch64/cpufunc.h:arm/cpufunc.h:

a baby step in the grand arm header unification challenge

Revision 1.56 / (download) - annotate - [select for diffs], Sat Oct 10 08:22:57 2020 UTC (2 years, 3 months ago) by jmcneill
Branch: MAIN
Branch point for: thorpej-futex
Changes since 1.55: +8 -4 lines
Diff to previous 1.55 (colored)

Fix detection of FP and SIMD features on Armv8.2+.

Revision 1.55 / (download) - annotate - [select for diffs], Wed Oct 7 16:03:10 2020 UTC (2 years, 3 months ago) by jmcneill
Branch: MAIN
Changes since 1.54: +9 -2 lines
Diff to previous 1.54 (colored)

Only touch PMC registers if Performance Monitor Extensions are present.

Revision 1.54 / (download) - annotate - [select for diffs], Sat Jul 25 22:51:57 2020 UTC (2 years, 6 months ago) by riastradh
Branch: MAIN
Changes since 1.53: +24 -2 lines
Diff to previous 1.53 (colored)

Implement ChaCha with NEON on ARM.

XXX Needs performance measurement.
XXX Needs adaptation to arm32 neon which has half the registers.

Revision 1.53 / (download) - annotate - [select for diffs], Sat Jul 25 22:12:56 2020 UTC (2 years, 6 months ago) by riastradh
Branch: MAIN
Changes since 1.52: +3 -2 lines
Diff to previous 1.52 (colored)

Split aes_impl declarations out into aes_impl.h.

This will make it less painful to add more operations to struct
aes_impl without having to recompile everything that just uses the
block cipher directly or similar.

Revision 1.52 / (download) - annotate - [select for diffs], Wed Jul 1 08:01:07 2020 UTC (2 years, 7 months ago) by ryo
Branch: MAIN
Changes since 1.51: +5 -2 lines
Diff to previous 1.51 (colored)

- On some systems with a different cache line size (and DIC,IDC) per CPU, trap "mrs Xt,ctr_el0" instruction
  to return the minimum cache line size of the system to userland.
- add CLIDR_EL1 and CTR_EL0 to struct aarch64_sysctl_cpu_id.

On most systems, cache line size is the same for all CPUs, so this mechanism won't be required.
Rather, this is primarily for errata support, which will be committed later.

Revision 1.51 / (download) - annotate - [select for diffs], Wed Jul 1 07:59:16 2020 UTC (2 years, 7 months ago) by ryo
Branch: MAIN
Changes since 1.50: +12 -5 lines
Diff to previous 1.50 (colored)

Switch the Icache sync operation to the necessary and sufficient one according to the CTR_EL0.DIC and CTR_EL0.IDC flags.

If CTR_EL0.DIC=1, Icache invalidation is not required.
If CTR_EL0.IDC=1, Dcache clean before Icache invalidation is not required.
CLIDR_EL1.LoC is 0, or CLIDR_EL1.LoUIS and CLIDR_EL1.LoUU are 0, Dcache clean is not required as well.

SEE ALSO ARMARM, "CTR_EL0 Cache Type Register", and "CLIDR_EL1 Cache Level ID Register"

Revision 1.50 / (download) - annotate - [select for diffs], Mon Jun 29 23:56:30 2020 UTC (2 years, 7 months ago) by riastradh
Branch: MAIN
Changes since 1.49: +15 -6 lines
Diff to previous 1.49 (colored)

New permutation-based AES implementation using ARM NEON.

Also derived from Mike Hamburg's public-domain vpaes code.

Revision 1.49 / (download) - annotate - [select for diffs], Mon Jun 29 23:31:41 2020 UTC (2 years, 7 months ago) by riastradh
Branch: MAIN
Changes since 1.48: +26 -2 lines
Diff to previous 1.48 (colored)

Implement AES in kernel using ARMv8.0-AES on aarch64.

Revision 1.48 / (download) - annotate - [select for diffs], Mon Jun 29 23:22:27 2020 UTC (2 years, 7 months ago) by riastradh
Branch: MAIN
Changes since 1.47: +4 -2 lines
Diff to previous 1.47 (colored)

Draft fpu_kern_enter/leave on aarch64.

Revision 1.47 / (download) - annotate - [select for diffs], Sun Jun 14 16:10:18 2020 UTC (2 years, 7 months ago) by riastradh
Branch: MAIN
Changes since 1.46: +18 -2 lines
Diff to previous 1.46 (colored)

Add some more id_aa64pfr0_el1 bits.

Revision 1.46 / (download) - annotate - [select for diffs], Sat May 30 17:50:39 2020 UTC (2 years, 8 months ago) by jmcneill
Branch: MAIN
Changes since 1.45: +3 -3 lines
Diff to previous 1.45 (colored)

sctlr_el1 and ctr_el0 are 64-bit registers

Revision 1.45 / (download) - annotate - [select for diffs], Mon May 11 14:44:16 2020 UTC (2 years, 8 months ago) by riastradh
Branch: MAIN
Changes since 1.44: +71 -2 lines
Diff to previous 1.44 (colored)

Add support for the ARMv8.5-RNG CPU random number generator.

We use the RNDRRS system register.  I made the following two
wild-arse guesses about the architecture of real implementations,
which might not exist yet:

1. There's only one physical source per CPU package, so not worth
   attaching one per core.

2. Like other CPU RNGs -- RDSEED, VIA C3 -- this probably gives about
   half a bit of entropy per bit of data (although perhaps we should
   say zero and revisit this once it arrives on real silicon).

Tested in qemu as well as I can, using `-cpu max' (which doesn't get
to userland for unrelated reasons).

This uses the numeric notation `mrs %0, s3_3_c2_c4_1' for the rndrrs
system register instead of the more legible `mrs %0, rndrrs' as
suggested in the ARMv8.5 ARM.  Why?

- clang doesn't like `mrs %0, rndrrs' for reasons unclear to me.

- gas only likes it with `.arch armv8.5-a+rng', but there's no clear
  way to keep that scoped; the `.set push/pop' stack that would be an
  obvious choice for this works only on mips.

- gcc supports __attribute__((target("arch=..."))) on functions, but
  the version we use doesn't yet know about armv8.5-a+rng.

Later on, we should replace this by a target attribute and the more
obvious `mrs %0, rndrrs' notation.

ok nick

Revision 1.44 / (download) - annotate - [select for diffs], Sun May 10 21:41:19 2020 UTC (2 years, 8 months ago) by riastradh
Branch: MAIN
Changes since 1.43: +7 -2 lines
Diff to previous 1.43 (colored)

Print RNDR support in verbose CPU feature identification.

Revision 1.1.4.2 / (download) - annotate - [select for diffs], Mon Apr 13 08:03:27 2020 UTC (2 years, 9 months ago) by martin
Branch: phil-wifi
Changes since 1.1.4.1: +104 -121 lines
Diff to previous 1.1.4.1 (colored) to branchpoint 1.1 (colored) next main 1.2 (colored)

Mostly merge changes from HEAD upto 20200411

Revision 1.43 / (download) - annotate - [select for diffs], Sun Apr 5 22:54:51 2020 UTC (2 years, 10 months ago) by jmcneill
Branch: MAIN
CVS Tags: phil-wifi-20200421, phil-wifi-20200411, phil-wifi-20200406, bouyer-xenpvh-base2, bouyer-xenpvh-base1, bouyer-xenpvh-base, bouyer-xenpvh
Changes since 1.42: +63 -65 lines
Diff to previous 1.42 (colored)

Cleanup CPU attach output:
 - Always print the core's vendor and product name.
 - Print the CPU ID on the same line as the name. Single line of dmesg
   per core.
 - Use aprint_verbose for reporting additional details.

Revision 1.42 / (download) - annotate - [select for diffs], Mon Mar 30 11:38:29 2020 UTC (2 years, 10 months ago) by jmcneill
Branch: MAIN
Changes since 1.41: +23 -4 lines
Diff to previous 1.41 (colored)

Enable the cycle counter when a CPU hatches and store an estimate of the
frequency in ci_data.cpu_cc_freq.

Revision 1.31.2.3 / (download) - annotate - [select for diffs], Sat Feb 29 20:18:15 2020 UTC (2 years, 11 months ago) by ad
Branch: ad-namecache
Changes since 1.31.2.2: +8 -67 lines
Diff to previous 1.31.2.2 (colored) to branchpoint 1.31 (colored) next main 1.32 (colored)

Sync with head.

Revision 1.41 / (download) - annotate - [select for diffs], Sat Feb 15 08:16:10 2020 UTC (2 years, 11 months ago) by skrll
Branch: MAIN
CVS Tags: is-mlppp-base, is-mlppp, ad-namecache-base3
Changes since 1.40: +4 -61 lines
Diff to previous 1.40 (colored)

Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
  drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
  - a static cpu_info_store array
  - the same arm_cpu_{hatched,mbox}

Revision 1.40 / (download) - annotate - [select for diffs], Sun Feb 9 08:14:55 2020 UTC (2 years, 11 months ago) by skrll
Branch: MAIN
Changes since 1.39: +4 -6 lines
Diff to previous 1.39 (colored)

#if 0 / #endif -> a comment

Revision 1.39 / (download) - annotate - [select for diffs], Tue Jan 28 17:47:50 2020 UTC (3 years ago) by maxv
Branch: MAIN
Changes since 1.38: +3 -4 lines
Diff to previous 1.38 (colored)

Fetch ID_AA64MMFR2_EL1. Okayed by Nick the other day.

Revision 1.38 / (download) - annotate - [select for diffs], Mon Jan 27 16:25:08 2020 UTC (3 years ago) by skrll
Branch: MAIN
Changes since 1.37: +3 -3 lines
Diff to previous 1.37 (colored)

NVIDIA's breakaway marketing dept have been in touch.

Revision 1.37 / (download) - annotate - [select for diffs], Mon Jan 27 12:56:44 2020 UTC (3 years ago) by skrll
Branch: MAIN
Changes since 1.36: +3 -2 lines
Diff to previous 1.36 (colored)

Identify the Denver2 CPU in the Nvidia TX2

Revision 1.31.2.2 / (download) - annotate - [select for diffs], Sat Jan 25 22:38:36 2020 UTC (3 years ago) by ad
Branch: ad-namecache
Changes since 1.31.2.1: +6 -6 lines
Diff to previous 1.31.2.1 (colored) to branchpoint 1.31 (colored)

Sync with head.

Revision 1.36 / (download) - annotate - [select for diffs], Sat Jan 25 18:18:31 2020 UTC (3 years ago) by skrll
Branch: MAIN
CVS Tags: ad-namecache-base2
Changes since 1.35: +4 -4 lines
Diff to previous 1.35 (colored)

Trailing whitespace

Revision 1.35 / (download) - annotate - [select for diffs], Mon Jan 20 12:32:04 2020 UTC (3 years ago) by skrll
Branch: MAIN
Changes since 1.34: +4 -4 lines
Diff to previous 1.34 (colored)

KNF

Revision 1.31.2.1 / (download) - annotate - [select for diffs], Fri Jan 17 21:47:22 2020 UTC (3 years ago) by ad
Branch: ad-namecache
Changes since 1.31: +13 -8 lines
Diff to previous 1.31 (colored)

Sync with head.

Revision 1.34 / (download) - annotate - [select for diffs], Wed Jan 15 08:34:04 2020 UTC (3 years ago) by mrg
Branch: MAIN
CVS Tags: ad-namecache-base1
Changes since 1.33: +4 -41 lines
Diff to previous 1.33 (colored)

port the arm64 cpu topology setup for big.little to arm.

rename arm64 cpu_do_topology() to arm_cpu_do_topology() and
call it from both arm cpu_attach().

replace both aarch64_set_topology() inline code in arm
cpu_attach() with new arm_cpu_do_topology(), which is called
by the arm64 locore as well (possibly not needed, which would
allow it to become static.)

not yet tested on a real big.little armv7 system.  tested
on rockpro64 and pinebook pro.

Revision 1.33 / (download) - annotate - [select for diffs], Sun Jan 12 09:29:18 2020 UTC (3 years ago) by mrg
Branch: MAIN
Changes since 1.32: +44 -6 lines
Diff to previous 1.32 (colored)

provide some semblance of valid cpu topology for big.little systems.

while attaching cpus, if the FDT provides "capacity-dmips-mhz" track
the fastest set, and call cpu_topology_set() with slow=true for any
cpus that are not the fastest.

bug fix for cpu_topology_set(): actually set ci_is_slow for slow cpus.

with this change, and -current's recent scheduler changes, this means
that long running processes run on the faster cores.  on RK3399 based
systems, i am seeing 20-50% speed ups for many tasks.


XXX: all this can be made common with armv7 big.little.

Revision 1.20.2.3 / (download) - annotate - [select for diffs], Thu Jan 9 17:16:47 2020 UTC (3 years ago) by snj
Branch: netbsd-9
CVS Tags: netbsd-9-3-RELEASE, netbsd-9-2-RELEASE, netbsd-9-1-RELEASE, netbsd-9-0-RELEASE, netbsd-9-0-RC2
Changes since 1.20.2.2: +8 -4 lines
Diff to previous 1.20.2.2 (colored) to branchpoint 1.20 (colored) next main 1.21 (colored)

Pull up following revision(s) (requested by martin in ticket #614):

	sys/arch/aarch64/aarch64/cpu.c: 1.32
	sys/arch/arm/arm32/cpu.c: 1.138
	sys/dev/fdt/fdtbus.c: 1.31

When attaching the first fdtbus, use the root "comptabile" (or failing that:
"model") property to set the cpu model (in userland aka sysctl hw.model).
When attaching the first cpu, do not overwrite a cpu model if it already
had been set.

Revision 1.32 / (download) - annotate - [select for diffs], Thu Jan 9 16:23:41 2020 UTC (3 years ago) by martin
Branch: MAIN
Changes since 1.31: +8 -4 lines
Diff to previous 1.31 (colored)

When attaching the first fdtbus, use the root "comptabile" (or failing that:
"model") property to set the cpu model (in userland aka sysctl hw.model).
When attaching the first cpu, do not overwrite a cpu model if it already
had been set.

Revision 1.20.2.2 / (download) - annotate - [select for diffs], Sun Dec 29 09:40:59 2019 UTC (3 years, 1 month ago) by martin
Branch: netbsd-9
Changes since 1.20.2.1: +4 -2 lines
Diff to previous 1.20.2.1 (colored) to branchpoint 1.20 (colored)

Pull up following revision(s) (requested by jmcneill in ticket #589):

	sys/arch/arm/include/cputypes.h: revision 1.11
	sys/arch/aarch64/aarch64/cpu.c: revision 1.31

Identify Arm Neoverse E1 and N1 CPUs.

Revision 1.31 / (download) - annotate - [select for diffs], Sat Dec 28 19:18:31 2019 UTC (3 years, 1 month ago) by jmcneill
Branch: MAIN
CVS Tags: ad-namecache-base
Branch point for: ad-namecache
Changes since 1.30: +4 -2 lines
Diff to previous 1.30 (colored)

Identify Arm Neoverse E1 and N1 CPUs.

Revision 1.30 / (download) - annotate - [select for diffs], Fri Dec 27 21:55:51 2019 UTC (3 years, 1 month ago) by mlelstv
Branch: MAIN
Changes since 1.29: +4 -3 lines
Diff to previous 1.29 (colored)

Fix build.

Revision 1.29 / (download) - annotate - [select for diffs], Fri Dec 27 15:36:02 2019 UTC (3 years, 1 month ago) by skrll
Branch: MAIN
Changes since 1.28: +3 -2 lines
Diff to previous 1.28 (colored)

Add a missing newline

Revision 1.28 / (download) - annotate - [select for diffs], Sat Dec 21 12:53:54 2019 UTC (3 years, 1 month ago) by ad
Branch: MAIN
Changes since 1.27: +4 -3 lines
Diff to previous 1.27 (colored)

Fix build break (ci->ci_dev is not available on every port).

Revision 1.27 / (download) - annotate - [select for diffs], Fri Dec 20 21:05:33 2019 UTC (3 years, 1 month ago) by ad
Branch: MAIN
Changes since 1.26: +3 -4 lines
Diff to previous 1.26 (colored)

Some more CPU topology stuff:

- Use cegger@'s ACPI SRAT parsing code to figure out NUMA node ID for each
  CPU as it is attached.

- For scheduler experiments with SMT, flag CPUs with the lowest numbered SMT
  IDs as "primaries", link back to the primaries from secondaries, and build
  a circular list of CPUs in each package with identical SMT IDs.

- No need for package/core/smt/numa IDs to be anything other than a u_int.

Revision 1.26 / (download) - annotate - [select for diffs], Fri Nov 22 05:21:19 2019 UTC (3 years, 2 months ago) by mlelstv
Branch: MAIN
Changes since 1.25: +9 -15 lines
Diff to previous 1.25 (colored)

Make cache operations available early.

Revision 1.20.2.1 / (download) - annotate - [select for diffs], Wed Oct 23 19:14:19 2019 UTC (3 years, 3 months ago) by martin
Branch: netbsd-9
CVS Tags: netbsd-9-0-RC1
Changes since 1.20: +32 -15 lines
Diff to previous 1.20 (colored)

Pull up following revision(s) (requested by jmcneill in ticket #359):

	sys/arch/aarch64/aarch64/locore.S: revision 1.42
	sys/arch/aarch64/aarch64/locore.S: revision 1.43
	sys/arch/aarch64/aarch64/locore.S: revision 1.44
	sys/arch/arm/fdt/cpu_fdt.c: revision 1.28
	sys/arch/aarch64/include/cpu.h: revision 1.14
	sys/arch/aarch64/include/param.h: revision 1.12
	sys/arch/arm/arm32/cpu.c: revision 1.133
	sys/arch/arm/arm32/cpu.c: revision 1.134
	sys/arch/arm/include/cpu.h: revision 1.101
	sys/arch/arm/acpi/cpu_acpi.c: revision 1.7
	sys/arch/aarch64/aarch64/cpu.c: revision 1.23
	sys/arch/aarch64/aarch64/cpu.c: revision 1.24
	sys/arch/aarch64/aarch64/cpu.c: revision 1.25

Increase aarch64 MAXCPUS to 256.

 -

Invalidate dcache before polling AP hatched status

 -

Avoid overlap between BP and last AP stack. AP stacks are now in order of
increasing address order.

Spotted by and idea from mlelstv.

 -

Use separate cacheline aligned arrays for mbox and hatched as before.

 -

cpu_hatched_p only for MULTIPROCESSOR

Revision 1.25 / (download) - annotate - [select for diffs], Sun Oct 20 14:03:51 2019 UTC (3 years, 3 months ago) by jmcneill
Branch: MAIN
CVS Tags: phil-wifi-20191119
Changes since 1.24: +21 -21 lines
Diff to previous 1.24 (colored)

Use separate cacheline aligned arrays for mbox and hatched as before.

Revision 1.24 / (download) - annotate - [select for diffs], Sun Oct 20 11:17:41 2019 UTC (3 years, 3 months ago) by jmcneill
Branch: MAIN
Changes since 1.23: +3 -3 lines
Diff to previous 1.23 (colored)

Invalidate dcache before polling AP hatched status

Revision 1.23 / (download) - annotate - [select for diffs], Sat Oct 19 18:04:26 2019 UTC (3 years, 3 months ago) by jmcneill
Branch: MAIN
Changes since 1.22: +32 -15 lines
Diff to previous 1.22 (colored)

Increase aarch64 MAXCPUS to 256.

Revision 1.22 / (download) - annotate - [select for diffs], Mon Oct 14 22:53:05 2019 UTC (3 years, 3 months ago) by jmcneill
Branch: MAIN
Changes since 1.21: +2 -10 lines
Diff to previous 1.21 (colored)

Remove the A72 errata #859971 detection, it causes an illegal instruction on AWS A1 (virtualized)

Revision 1.21 / (download) - annotate - [select for diffs], Sun Sep 15 15:16:30 2019 UTC (3 years, 4 months ago) by tnn
Branch: MAIN
Changes since 1.20: +10 -2 lines
Diff to previous 1.20 (colored)

report A72 errata #859971 workaround status during boot

Revision 1.20 / (download) - annotate - [select for diffs], Tue Jul 16 20:29:53 2019 UTC (3 years, 6 months ago) by jmcneill
Branch: MAIN
CVS Tags: netbsd-9-base
Branch point for: netbsd-9
Changes since 1.19: +3 -3 lines
Diff to previous 1.19 (colored)

Need CPU_PARTMASK for eMAG CPU ID

Revision 1.19 / (download) - annotate - [select for diffs], Tue Jul 16 10:37:12 2019 UTC (3 years, 6 months ago) by jmcneill
Branch: MAIN
Changes since 1.18: +3 -2 lines
Diff to previous 1.18 (colored)

Add Ampere eMAG 8180 cpuid

Revision 1.18 / (download) - annotate - [select for diffs], Wed Jun 19 05:31:05 2019 UTC (3 years, 7 months ago) by mrg
Branch: MAIN
Changes since 1.17: +9 -5 lines
Diff to previous 1.17 (colored)

add several cortex CPU implementations found in their TRMs:
- A32 R1 (aarch32 only, not supported)
- A35 R1
- A65 R0
- A76AE R1
- A77

add the aarch64 ones to cpu.c for identification.

Revision 1.1.4.1 / (download) - annotate - [select for diffs], Mon Jun 10 22:05:42 2019 UTC (3 years, 7 months ago) by christos
Branch: phil-wifi
Changes since 1.1: +261 -156 lines
Diff to previous 1.1 (colored)

Sync with HEAD

Revision 1.17 / (download) - annotate - [select for diffs], Thu May 9 07:38:44 2019 UTC (3 years, 8 months ago) by mrg
Branch: MAIN
CVS Tags: phil-wifi-20190609
Changes since 1.16: +3 -2 lines
Diff to previous 1.16 (colored)

add cortex A-76 detection.

Revision 1.1.2.9 / (download) - annotate - [select for diffs], Sat Jan 26 21:59:58 2019 UTC (4 years ago) by pgoyette
Branch: pgoyette-compat
CVS Tags: pgoyette-compat-merge-20190127
Changes since 1.1.2.8: +7 -7 lines
Diff to previous 1.1.2.8 (colored) to branchpoint 1.1 (colored) next main 1.2 (colored)

Sync with HEAD

Revision 1.16 / (download) - annotate - [select for diffs], Mon Jan 21 08:04:26 2019 UTC (4 years ago) by skrll
Branch: MAIN
CVS Tags: pgoyette-compat-20190127, isaki-audio2-base, isaki-audio2
Changes since 1.15: +7 -7 lines
Diff to previous 1.15 (colored)

Use ci_{package,core,smt}_id instead of ci_data.cpu_{package,core,smt}_id

NFC

Revision 1.1.2.8 / (download) - annotate - [select for diffs], Wed Dec 26 14:01:30 2018 UTC (4 years, 1 month ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1.2.7: +14 -2 lines
Diff to previous 1.1.2.7 (colored) to branchpoint 1.1 (colored)

Sync with HEAD, resolve a few conflicts

Revision 1.15 / (download) - annotate - [select for diffs], Fri Dec 21 08:01:01 2018 UTC (4 years, 1 month ago) by ryo
Branch: MAIN
CVS Tags: pgoyette-compat-20190118, pgoyette-compat-1226
Changes since 1.14: +4 -2 lines
Diff to previous 1.14 (colored)

- add workaround for Cavium ThunderX errata 27456.
- add cpufuncs table in cpu_info. each cpu clusters may have different erratum. (e.g. big.LITTLE)

Revision 1.14 / (download) - annotate - [select for diffs], Wed Nov 28 09:16:19 2018 UTC (4 years, 2 months ago) by ryo
Branch: MAIN
Changes since 1.13: +12 -2 lines
Diff to previous 1.13 (colored)

support boot option "-1" to disable multiprocessor boot, and "-z" to set AB_SILENT flag.

Revision 1.1.2.7 / (download) - annotate - [select for diffs], Mon Nov 26 01:52:16 2018 UTC (4 years, 2 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1.2.6: +98 -38 lines
Diff to previous 1.1.2.6 (colored) to branchpoint 1.1 (colored)

Sync with HEAD, resolve a couple of conflicts

Revision 1.13 / (download) - annotate - [select for diffs], Tue Nov 20 01:59:51 2018 UTC (4 years, 2 months ago) by mrg
Branch: MAIN
CVS Tags: pgoyette-compat-1126
Changes since 1.12: +98 -38 lines
Diff to previous 1.12 (colored)

rewrite the CPU identification on arm64:

- publish per-cpu data
- publish a whole bunch of info in struct aarch64_sysctl_cpu_id
  instead of various individual nodes (there are 16 total.)
- add MIDR extractor bits
- define ARMv8.2-A id_aa64mmfr2_el1 and id_aa64zfr0_el1 regs,
  but avoid using them until we make sure they exist.  (these
  members are added to aarch64_sysctl_cpu_id to avoid future
  compat issues.)

the arm32 and aarch32 version of these need to be adjusted as
well (and aarch32 data published at all.)  still trying to
work out how to make the same userland binary running on a
real arm32 or an aarch32 system can work sanely here.

ok ryo@.

Revision 1.1.2.6 / (download) - annotate - [select for diffs], Sat Oct 20 06:58:23 2018 UTC (4 years, 3 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1.2.5: +8 -6 lines
Diff to previous 1.1.2.5 (colored) to branchpoint 1.1 (colored)

Sync with head

Revision 1.12 / (download) - annotate - [select for diffs], Sun Oct 14 14:31:05 2018 UTC (4 years, 3 months ago) by skrll
Branch: MAIN
CVS Tags: pgoyette-compat-1020
Changes since 1.11: +3 -3 lines
Diff to previous 1.11 (colored)

Use __nothing

Revision 1.11 / (download) - annotate - [select for diffs], Thu Oct 4 07:36:10 2018 UTC (4 years, 4 months ago) by ryo
Branch: MAIN
Changes since 1.10: +2 -4 lines
Diff to previous 1.10 (colored)

remove XXX delay to attach cpus in order

Revision 1.10 / (download) - annotate - [select for diffs], Wed Oct 3 13:59:31 2018 UTC (4 years, 4 months ago) by skrll
Branch: MAIN
Changes since 1.9: +3 -3 lines
Diff to previous 1.9 (colored)

Another space that hurts Jared's eyes.

Revision 1.9 / (download) - annotate - [select for diffs], Wed Oct 3 09:59:05 2018 UTC (4 years, 4 months ago) by skrll
Branch: MAIN
Changes since 1.8: +6 -6 lines
Diff to previous 1.8 (colored)

Fix some product names and details as suggested by jmcneill

Revision 1.8 / (download) - annotate - [select for diffs], Wed Oct 3 05:49:53 2018 UTC (4 years, 4 months ago) by skrll
Branch: MAIN
Changes since 1.7: +7 -3 lines
Diff to previous 1.7 (colored)

Identify some Cavium ThunderX CPUs

Revision 1.1.2.5 / (download) - annotate - [select for diffs], Sun Sep 30 01:45:35 2018 UTC (4 years, 4 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1.2.4: +4 -3 lines
Diff to previous 1.1.2.4 (colored) to branchpoint 1.1 (colored)

Ssync with HEAD

Revision 1.7 / (download) - annotate - [select for diffs], Mon Sep 10 11:05:12 2018 UTC (4 years, 4 months ago) by ryo
Branch: MAIN
CVS Tags: pgoyette-compat-0930
Changes since 1.6: +4 -3 lines
Diff to previous 1.6 (colored)

cleanup aarch64 mpstart and fdt bootstrap
 * arm_cpu_hatch_arg is a bad idea. avoid serializing CPU startup, and eliminate arm_cpu_hatch_arg.
   in mpstart, resolve own cpu index using array of cpu_mpidr[] (aarch64)
 * add support fdt enable-method "spin-table"
 * add support fdt enable-method "brcm,bcm2836-smp" (for 32bit RaspberryPi)
 * use arm_fdt_cpu_bootstrap() instead of psci_fdt_bootstrap()
 * rename "arm/fdt/psci_fdt.h" to "arm/fdt/psci_fdtvar.h" because of conflict of include file for needs-flag
 * add devmap for cpu spin-table of raspberrypi3/aarch64
 * no need to force hatch APs for raspberrypi3/arm32 ifndef MULTIPROCESSOR.
 * fix to work pmap_extract(kerneltext/data/bss) even if before calling pmap_bootstrap

idea to use cpu_mpidr[] by jmcneill@. reviewd by skrll@. thanks.

Revision 1.1.2.4 / (download) - annotate - [select for diffs], Thu Sep 6 06:55:22 2018 UTC (4 years, 5 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1.2.3: +61 -131 lines
Diff to previous 1.1.2.3 (colored) to branchpoint 1.1 (colored)

Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)

Revision 1.6 / (download) - annotate - [select for diffs], Sun Aug 26 18:15:49 2018 UTC (4 years, 5 months ago) by ryo
Branch: MAIN
CVS Tags: pgoyette-compat-0906
Changes since 1.5: +48 -120 lines
Diff to previous 1.5 (colored)

add support multiple cpu clusters.
* pass cpu index as an argument to secondary processors when hatching.
* keep cpu cache confituration per cpu clusters.

Hello big.LITTLE!

Revision 1.5 / (download) - annotate - [select for diffs], Mon Aug 20 18:13:56 2018 UTC (4 years, 5 months ago) by jmcneill
Branch: MAIN
Changes since 1.4: +7 -7 lines
Diff to previous 1.4 (colored)

Use __SHIFTOUT to extract MPIDR affinity levels

Revision 1.4 / (download) - annotate - [select for diffs], Tue Jul 31 07:00:48 2018 UTC (4 years, 6 months ago) by skrll
Branch: MAIN
Changes since 1.3: +10 -8 lines
Diff to previous 1.3 (colored)

Define and use VPRINTF

Revision 1.1.2.3 / (download) - annotate - [select for diffs], Sat Jul 28 04:37:25 2018 UTC (4 years, 6 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1.2.2: +147 -48 lines
Diff to previous 1.1.2.2 (colored) to branchpoint 1.1 (colored)

Sync with HEAD

Revision 1.3 / (download) - annotate - [select for diffs], Tue Jul 17 00:29:55 2018 UTC (4 years, 6 months ago) by christos
Branch: MAIN
CVS Tags: pgoyette-compat-0728
Changes since 1.2: +13 -6 lines
Diff to previous 1.2 (colored)

add default statements, use PRI?64 instead of ll?

Revision 1.2 / (download) - annotate - [select for diffs], Mon Jul 9 06:19:53 2018 UTC (4 years, 6 months ago) by ryo
Branch: MAIN
Changes since 1.1: +136 -44 lines
Diff to previous 1.1 (colored)

add MULTIPROCESSOR support

Revision 1.1.2.2 / (download) - annotate - [select for diffs], Sat Apr 7 04:12:10 2018 UTC (4 years, 10 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1.2.1: +450 -0 lines
Diff to previous 1.1.2.1 (colored) to branchpoint 1.1 (colored)

Sync with HEAD.  77 conflicts resolved - all of them $NetBSD$

Revision 1.1.2.1, Sun Apr 1 04:35:03 2018 UTC (4 years, 10 months ago) by pgoyette
Branch: pgoyette-compat
Changes since 1.1: +0 -450 lines
FILE REMOVED

file cpu.c was added on branch pgoyette-compat on 2018-04-07 04:12:10 +0000

Revision 1.1 / (download) - annotate - [select for diffs], Sun Apr 1 04:35:03 2018 UTC (4 years, 10 months ago) by ryo
Branch: MAIN
CVS Tags: phil-wifi-base, pgoyette-compat-0625, pgoyette-compat-0521, pgoyette-compat-0502, pgoyette-compat-0422, pgoyette-compat-0415, pgoyette-compat-0407
Branch point for: phil-wifi, pgoyette-compat

Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)

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