version 1.44, 2017/12/01 22:47:06 |
version 1.44.2.1, 2018/07/28 04:37:22 |
Line 1704 arena_run_reg_alloc(arena_run_t *run, ar |
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Line 1704 arena_run_reg_alloc(arena_run_t *run, ar |
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+ (bin->reg_size * regind)); |
+ (bin->reg_size * regind)); |
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/* Clear bit. */ |
/* Clear bit. */ |
mask ^= (1 << bit); |
mask ^= (1U << bit); |
run->regs_mask[i] = mask; |
run->regs_mask[i] = mask; |
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return (ret); |
return (ret); |
Line 1721 arena_run_reg_alloc(arena_run_t *run, ar |
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Line 1721 arena_run_reg_alloc(arena_run_t *run, ar |
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+ (bin->reg_size * regind)); |
+ (bin->reg_size * regind)); |
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/* Clear bit. */ |
/* Clear bit. */ |
mask ^= (1 << bit); |
mask ^= (1U << bit); |
run->regs_mask[i] = mask; |
run->regs_mask[i] = mask; |
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/* |
/* |
Line 1836 arena_run_reg_dalloc(arena_run_t *run, a |
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Line 1836 arena_run_reg_dalloc(arena_run_t *run, a |
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if (elm < run->regs_minelm) |
if (elm < run->regs_minelm) |
run->regs_minelm = elm; |
run->regs_minelm = elm; |
bit = regind - (elm << (SIZEOF_INT_2POW + 3)); |
bit = regind - (elm << (SIZEOF_INT_2POW + 3)); |
assert((run->regs_mask[elm] & (1 << bit)) == 0); |
assert((run->regs_mask[elm] & (1U << bit)) == 0); |
run->regs_mask[elm] |= (1 << bit); |
run->regs_mask[elm] |= (1U << bit); |
#undef SIZE_INV |
#undef SIZE_INV |
#undef SIZE_INV_SHIFT |
#undef SIZE_INV_SHIFT |
} |
} |