version 1.1.1.1.2.1, 2020/04/03 17:41:56 |
version 1.1.1.1.2.2, 2020/04/08 14:06:02 |
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/* TI PRU opcode list. |
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Copyright (C) 2014-2018 Free Software Foundation, Inc. |
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Contributed by Dimitar Dimitrov <dimitar@dinux.eu> |
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This file is part of the GNU opcodes library. |
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This library is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 3, or (at your option) |
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any later version. |
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It is distributed in the hope that it will be useful, but WITHOUT |
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
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License for more details. |
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You should have received a copy of the GNU General Public License |
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along with this file; see the file COPYING. If not, write to the |
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
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MA 02110-1301, USA. */ |
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/* Source: |
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http://processors.wiki.ti.com/index.php/Programmable_Realtime_Unit */ |
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#include "sysdep.h" |
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#include <stdio.h> |
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#include "opcode/pru.h" |
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/* Register string table. */ |
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#define DECLARE_REG(name, index) \ |
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{ #name ".b0", (index), RSEL_7_0 }, \ |
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{ #name ".b1", (index), RSEL_15_8 }, \ |
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{ #name ".b2", (index), RSEL_23_16 }, \ |
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{ #name ".b3", (index), RSEL_31_24 }, \ |
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{ #name ".w0", (index), RSEL_15_0 }, \ |
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{ #name ".w1", (index), RSEL_23_8 }, \ |
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{ #name ".w2", (index), RSEL_31_16 }, \ |
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{ #name , (index), RSEL_31_0 } |
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const struct pru_reg pru_regs[] = { |
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/* Standard register names. */ |
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DECLARE_REG (r0, 0), |
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DECLARE_REG (r1, 1), |
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DECLARE_REG (sp, 2), /* Stack pointer. */ |
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DECLARE_REG (ra, 3), /* Return address. */ |
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DECLARE_REG (fp, 4), /* Frame pointer. */ |
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DECLARE_REG (r5, 5), |
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DECLARE_REG (r6, 6), |
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DECLARE_REG (r7, 7), |
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DECLARE_REG (r8, 8), |
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DECLARE_REG (r9, 9), |
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DECLARE_REG (r10, 10), |
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DECLARE_REG (r11, 11), |
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DECLARE_REG (r12, 12), |
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DECLARE_REG (r13, 13), |
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DECLARE_REG (r14, 14), |
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DECLARE_REG (r15, 15), |
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DECLARE_REG (r16, 16), |
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DECLARE_REG (r17, 17), |
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DECLARE_REG (r18, 18), |
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DECLARE_REG (r19, 19), |
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DECLARE_REG (r20, 20), |
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DECLARE_REG (r21, 21), |
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DECLARE_REG (r22, 22), |
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DECLARE_REG (r23, 23), |
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DECLARE_REG (r24, 24), |
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DECLARE_REG (r25, 25), |
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DECLARE_REG (r26, 26), |
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DECLARE_REG (r27, 27), |
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DECLARE_REG (r28, 28), |
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DECLARE_REG (r29, 29), |
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DECLARE_REG (r30, 30), |
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DECLARE_REG (r31, 31), |
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/* Alternative names for special registers. */ |
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DECLARE_REG (r2, 2), |
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DECLARE_REG (r3, 3), |
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DECLARE_REG (r4, 4) |
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}; |
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#define PRU_NUM_REGS \ |
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((sizeof pru_regs) / (sizeof (pru_regs[0]))) |
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const int pru_num_regs = PRU_NUM_REGS; |
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#undef PRU_NUM_REGS |
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/* This is the opcode table used by the PRU GNU as and disassembler. */ |
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const struct pru_opcode pru_opcodes[] = |
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{ |
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/* { name, args, |
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match, mask, pinfo, overflow_msg } */ |
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#define DECLARE_FORMAT1_OPCODE(str, subop) \ |
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{ #str, prui_ ## str, "d,s,b", \ |
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OP_MATCH_ ## subop, OP_MASK_FMT1_OP | OP_MASK_SUBOP, 0, \ |
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unsigned_immed8_overflow } |
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DECLARE_FORMAT1_OPCODE (add, ADD), |
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DECLARE_FORMAT1_OPCODE (adc, ADC), |
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DECLARE_FORMAT1_OPCODE (sub, SUB), |
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DECLARE_FORMAT1_OPCODE (suc, SUC), |
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DECLARE_FORMAT1_OPCODE (lsl, LSL), |
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DECLARE_FORMAT1_OPCODE (lsr, LSR), |
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DECLARE_FORMAT1_OPCODE (rsb, RSB), |
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DECLARE_FORMAT1_OPCODE (rsc, RSC), |
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DECLARE_FORMAT1_OPCODE (and, AND), |
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DECLARE_FORMAT1_OPCODE (or, OR), |
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DECLARE_FORMAT1_OPCODE (xor, XOR), |
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DECLARE_FORMAT1_OPCODE (min, MIN), |
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DECLARE_FORMAT1_OPCODE (max, MAX), |
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DECLARE_FORMAT1_OPCODE (clr, CLR), |
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DECLARE_FORMAT1_OPCODE (set, SET), |
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{ "not", prui_not, "d,s", |
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OP_MATCH_NOT | OP_MASK_IO, |
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OP_MASK_FMT1_OP | OP_MASK_SUBOP | OP_MASK_IO, 0, no_overflow}, |
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{ "jmp", prui_jmp, "j", |
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OP_MATCH_JMP, OP_MASK_FMT2_OP | OP_MASK_SUBOP, 0, unsigned_immed16_overflow}, |
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{ "jal", prui_jal, "d,j", |
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OP_MATCH_JAL, OP_MASK_FMT2_OP | OP_MASK_SUBOP, 0, unsigned_immed16_overflow}, |
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{ "ldi", prui_ldi, "d,W", |
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OP_MATCH_LDI, OP_MASK_FMT2_OP | OP_MASK_SUBOP, 0, unsigned_immed16_overflow}, |
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{ "halt", prui_halt, "", |
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OP_MATCH_HALT, OP_MASK_FMT2_OP | OP_MASK_SUBOP, 0, no_overflow}, |
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{ "slp", prui_slp, "w", |
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OP_MATCH_SLP, OP_MASK_FMT2_OP | OP_MASK_SUBOP, 0, no_overflow}, |
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{ "xin", prui_xin, "x,D,n", |
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OP_MATCH_XIN, OP_MASK_XFR_OP, 0, unsigned_immed8_overflow}, |
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{ "xout", prui_xout, "x,D,n", |
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OP_MATCH_XOUT, OP_MASK_XFR_OP, 0, unsigned_immed8_overflow}, |
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{ "xchg", prui_xchg, "x,D,n", |
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OP_MATCH_XCHG, OP_MASK_XFR_OP, 0, unsigned_immed8_overflow}, |
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{ "sxin", prui_sxin, "x,D,n", |
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OP_MATCH_SXIN, OP_MASK_XFR_OP, 0, unsigned_immed8_overflow}, |
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{ "sxout", prui_sxout, "x,D,n", |
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OP_MATCH_SXOUT, OP_MASK_XFR_OP, 0, unsigned_immed8_overflow}, |
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{ "sxchg", prui_sxchg, "x,D,n", |
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OP_MATCH_SXCHG, OP_MASK_XFR_OP, 0, unsigned_immed8_overflow}, |
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{ "loop", prui_loop, "O,B", |
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OP_MATCH_LOOP, OP_MASK_LOOP_OP, 0, unsigned_immed8_overflow}, |
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{ "iloop", prui_loop, "O,B", |
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OP_MATCH_ILOOP, OP_MASK_LOOP_OP, 0, unsigned_immed8_overflow}, |
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{ "qbgt", prui_qbgt, "o,s,b", |
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OP_MATCH_QBGT, OP_MASK_FMT4_OP | OP_MASK_CMP, 0, qbranch_target_overflow}, |
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{ "qbge", prui_qbge, "o,s,b", |
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OP_MATCH_QBGE, OP_MASK_FMT4_OP | OP_MASK_CMP, 0, qbranch_target_overflow}, |
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{ "qblt", prui_qblt, "o,s,b", |
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OP_MATCH_QBLT, OP_MASK_FMT4_OP | OP_MASK_CMP, 0, qbranch_target_overflow}, |
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{ "qble", prui_qble, "o,s,b", |
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OP_MATCH_QBLE, OP_MASK_FMT4_OP | OP_MASK_CMP, 0, qbranch_target_overflow}, |
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{ "qbeq", prui_qbeq, "o,s,b", |
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OP_MATCH_QBEQ, OP_MASK_FMT4_OP | OP_MASK_CMP, 0, qbranch_target_overflow}, |
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{ "qbne", prui_qbne, "o,s,b", |
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OP_MATCH_QBNE, OP_MASK_FMT4_OP | OP_MASK_CMP, 0, qbranch_target_overflow}, |
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{ "qba", prui_qba, "o", |
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OP_MATCH_QBA, OP_MASK_FMT4_OP | OP_MASK_CMP, 0, qbranch_target_overflow}, |
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{ "qbbs", prui_qbbs, "o,s,b", |
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OP_MATCH_QBBS, OP_MASK_FMT5_OP | OP_MASK_BCMP, 0, qbranch_target_overflow}, |
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{ "qbbc", prui_qbbc, "o,s,b", |
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OP_MATCH_QBBC, OP_MASK_FMT5_OP | OP_MASK_BCMP, 0, qbranch_target_overflow}, |
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{ "lbbo", prui_lbbo, "D,S,b,l", |
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OP_MATCH_LBBO, OP_MASK_FMT6AB_OP | OP_MASK_LOADSTORE, 0, |
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unsigned_immed8_overflow}, |
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{ "sbbo", prui_sbbo, "D,S,b,l", |
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OP_MATCH_SBBO, OP_MASK_FMT6AB_OP | OP_MASK_LOADSTORE, 0, |
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unsigned_immed8_overflow}, |
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{ "lbco", prui_lbco, "D,c,b,l", |
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OP_MATCH_LBCO, OP_MASK_FMT6CD_OP | OP_MASK_LOADSTORE, 0, |
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unsigned_immed8_overflow}, |
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{ "sbco", prui_sbco, "D,c,b,l", |
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OP_MATCH_SBCO, OP_MASK_FMT6CD_OP | OP_MASK_LOADSTORE, 0, |
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unsigned_immed8_overflow}, |
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/* Fill in the default values for the real-instruction arguments. |
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The assembler will not do it! */ |
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{ "nop", prui_or, "", |
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OP_MATCH_OR |
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| (RSEL_31_0 << OP_SH_RS2SEL) | (0 << OP_SH_RS2) |
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| (RSEL_31_0 << OP_SH_RS1SEL) | (0 << OP_SH_RS1) |
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| (RSEL_31_0 << OP_SH_RDSEL) | (0 << OP_SH_RD), |
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OP_MASK_FMT1_OP | OP_MASK_SUBOP |
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| OP_MASK_RS2SEL | OP_MASK_RS2 | OP_MASK_RS1SEL | OP_MASK_RS1 |
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| OP_MASK_RDSEL | OP_MASK_RD | OP_MASK_IO, |
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PRU_INSN_MACRO, no_overflow}, |
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{ "mov", prui_or, "d,s", |
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OP_MATCH_OR | (0 << OP_SH_IMM8) | OP_MASK_IO, |
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OP_MASK_FMT1_OP | OP_MASK_SUBOP | OP_MASK_IMM8 | OP_MASK_IO, |
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PRU_INSN_MACRO, no_overflow}, |
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{ "ret", prui_jmp, "", |
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OP_MATCH_JMP |
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| (RSEL_31_16 << OP_SH_RS2SEL) | (3 << OP_SH_RS2), |
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OP_MASK_FMT2_OP | OP_MASK_SUBOP |
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| OP_MASK_RS2SEL | OP_MASK_RS2 | OP_MASK_IO, |
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PRU_INSN_MACRO, unsigned_immed16_overflow}, |
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{ "call", prui_jal, "j", |
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OP_MATCH_JAL |
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| (RSEL_31_16 << OP_SH_RDSEL) | (3 << OP_SH_RD), |
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OP_MASK_FMT2_OP | OP_MASK_SUBOP |
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| OP_MASK_RDSEL | OP_MASK_RD, |
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PRU_INSN_MACRO, unsigned_immed16_overflow}, |
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{ "wbc", prui_qbbs, "s,b", |
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OP_MATCH_QBBS | (0 << OP_SH_BROFF98) | (0 << OP_SH_BROFF70), |
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OP_MASK_FMT5_OP | OP_MASK_BCMP | OP_MASK_BROFF, |
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PRU_INSN_MACRO, qbranch_target_overflow}, |
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{ "wbs", prui_qbbc, "s,b", |
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OP_MATCH_QBBC | (0 << OP_SH_BROFF98) | (0 << OP_SH_BROFF70), |
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OP_MASK_FMT5_OP | OP_MASK_BCMP | OP_MASK_BROFF, |
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PRU_INSN_MACRO, qbranch_target_overflow}, |
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{ "fill", prui_xin, "D,n", |
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OP_MATCH_XIN | (254 << OP_SH_XFR_WBA), |
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OP_MASK_XFR_OP | OP_MASK_XFR_WBA, |
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PRU_INSN_MACRO, unsigned_immed8_overflow}, |
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{ "zero", prui_xin, "D,n", |
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OP_MATCH_XIN | (255 << OP_SH_XFR_WBA), |
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OP_MASK_XFR_OP | OP_MASK_XFR_WBA, |
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PRU_INSN_MACRO, unsigned_immed8_overflow}, |
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{ "ldi32", prui_ldi, "R,i", |
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OP_MATCH_LDI, OP_MASK_FMT2_OP | OP_MASK_SUBOP, |
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PRU_INSN_LDI32, unsigned_immed32_overflow}, |
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}; |
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#define PRU_NUM_OPCODES \ |
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((sizeof pru_opcodes) / (sizeof (pru_opcodes[0]))) |
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const int bfd_pru_num_opcodes = PRU_NUM_OPCODES; |
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#undef PRU_NUM_OPCODES |