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Annotation of src/external/gpl3/binutils.old/dist/opcodes/ia64-opc-a.c, Revision 1.1.1.5

1.1       christos    1: /* ia64-opc-a.c -- IA-64 `A' opcode table.
1.1.1.5 ! christos    2:    Copyright (C) 1998-2020 Free Software Foundation, Inc.
1.1       christos    3:    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
                      4:
                      5:    This file is part of the GNU opcodes library.
                      6:
                      7:    This library is free software; you can redistribute it and/or modify
                      8:    it under the terms of the GNU General Public License as published by
                      9:    the Free Software Foundation; either version 3, or (at your option)
                     10:    any later version.
                     11:
                     12:    It is distributed in the hope that it will be useful, but WITHOUT
                     13:    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
                     14:    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
                     15:    License for more details.
                     16:
                     17:    You should have received a copy of the GNU General Public License
                     18:    along with this file; see the file COPYING.  If not, write to the
                     19:    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
                     20:    MA 02110-1301, USA.  */
                     21:
                     22: #include "ia64-opc.h"
                     23:
                     24: #define A      IA64_TYPE_A, 1
                     25: #define A2     IA64_TYPE_A, 2
                     26:
                     27: /* instruction bit fields: */
                     28: #define bC(x)          (((ia64_insn) ((x) & 0x1)) << 12)
                     29: #define bImm14(x)      ((((ia64_insn) (((x) >>  0) & 0x7f)) << 13) | \
                     30:                         (((ia64_insn) (((x) >>  7) & 0x3f)) << 27) | \
                     31:                         (((ia64_insn) (((x) >> 13) & 0x01)) << 36))
                     32: #define bR3a(x)                (((ia64_insn) ((x) & 0x7f)) << 20)
                     33: #define bR3b(x)                (((ia64_insn) ((x) & 0x3)) << 20)
                     34: #define bTa(x)         (((ia64_insn) ((x) & 0x1)) << 33)
                     35: #define bTb(x)         (((ia64_insn) ((x) & 0x1)) << 36)
                     36: #define bVe(x)         (((ia64_insn) ((x) & 0x1)) << 33)
                     37: #define bX(x)          (((ia64_insn) ((x) & 0x1)) << 33)
                     38: #define bX2(x)         (((ia64_insn) ((x) & 0x3)) << 34)
                     39: #define bX2a(x)                (((ia64_insn) ((x) & 0x3)) << 34)
                     40: #define bX2b(x)                (((ia64_insn) ((x) & 0x3)) << 27)
                     41: #define bX4(x)         (((ia64_insn) ((x) & 0xf)) << 29)
                     42: #define bZa(x)         (((ia64_insn) ((x) & 0x1)) << 36)
                     43: #define bZb(x)         (((ia64_insn) ((x) & 0x1)) << 33)
                     44:
                     45: /* instruction bit masks: */
                     46: #define mC     bC (-1)
                     47: #define mImm14 bImm14 (-1)
                     48: #define mR3a   bR3a (-1)
                     49: #define mR3b   bR3b (-1)
                     50: #define mTa    bTa (-1)
                     51: #define mTb    bTb (-1)
                     52: #define mVe    bVe (-1)
                     53: #define mX     bX (-1)
                     54: #define mX2    bX2 (-1)
                     55: #define mX2a   bX2a (-1)
                     56: #define mX2b   bX2b (-1)
                     57: #define mX4    bX4 (-1)
                     58: #define mZa    bZa (-1)
                     59: #define mZb    bZb (-1)
                     60:
                     61: #define OpR3b(a,b)             (bOp (a) | bR3b (b)), (mOp | mR3b)
                     62: #define OpX2aVe(a,b,c)         (bOp (a) | bX2a (b) | bVe (c)), \
                     63:                                (mOp | mX2a | mVe)
                     64: #define OpX2aVeR3a(a,b,c,d)    (bOp (a) | bX2a (b) | bVe (c) | bR3a (d)), \
                     65:                                (mOp | mX2a | mVe | mR3a)
                     66: #define OpX2aVeImm14(a,b,c,d)  (bOp (a) | bX2a (b) | bVe (c) | bImm14 (d)), \
                     67:                                (mOp | mX2a | mVe | mImm14)
                     68: #define OpX2aVeX4(a,b,c,d)     (bOp (a) | bX2a (b) | bVe (c) | bX4 (d)), \
                     69:                                (mOp | mX2a | mVe | mX4)
                     70: #define OpX2aVeX4X2b(a,b,c,d,e)        \
                     71:        (bOp (a) | bX2a (b) | bVe (c) | bX4 (d) | bX2b (e)), \
                     72:        (mOp | mX2a | mVe | mX4 | mX2b)
                     73: #define OpX2TbTaC(a,b,c,d,e) \
                     74:        (bOp (a) | bX2 (b) | bTb (c) | bTa (d) | bC (e)), \
                     75:        (mOp | mX2 | mTb | mTa | mC)
                     76: #define OpX2TaC(a,b,c,d)       (bOp (a) | bX2 (b) | bTa (c) | bC (d)), \
                     77:                                (mOp | mX2 | mTa | mC)
                     78: #define OpX2aZaZbX4(a,b,c,d,e) \
                     79:        (bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e)), \
                     80:        (mOp | mX2a | mZa | mZb | mX4)
                     81: #define OpX2aZaZbX4X2b(a,b,c,d,e,f) \
                     82:        (bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e) | bX2b (f)), \
                     83:        (mOp | mX2a | mZa | mZb | mX4 | mX2b)
                     84:
                     85: /* Used to initialise unused fields in ia64_opcode struct,
                     86:    in order to stop gcc from complaining.  */
                     87: #define EMPTY 0,0,NULL
                     88:
                     89: struct ia64_opcode ia64_opcodes_a[] =
                     90:   {
                     91:     /* A-type instruction encodings (sorted according to major opcode).  */
                     92:
                     93:     {"add",     A, OpX2aVeX4X2b (8, 0, 0, 0, 0), {R1, R2, R3}, EMPTY},
                     94:     {"add",     A, OpX2aVeX4X2b (8, 0, 0, 0, 1), {R1, R2, R3, C1}, EMPTY},
                     95:     {"sub",     A, OpX2aVeX4X2b (8, 0, 0, 1, 1), {R1, R2, R3}, EMPTY},
                     96:     {"sub",     A, OpX2aVeX4X2b (8, 0, 0, 1, 0), {R1, R2, R3, C1}, EMPTY},
                     97:     {"addp4",   A, OpX2aVeX4X2b (8, 0, 0, 2, 0), {R1, R2, R3}, EMPTY},
                     98:     {"and",     A, OpX2aVeX4X2b (8, 0, 0, 3, 0), {R1, R2, R3}, EMPTY},
                     99:     {"andcm",   A, OpX2aVeX4X2b (8, 0, 0, 3, 1), {R1, R2, R3}, EMPTY},
                    100:     {"or",      A, OpX2aVeX4X2b (8, 0, 0, 3, 2), {R1, R2, R3}, EMPTY},
                    101:     {"xor",     A, OpX2aVeX4X2b (8, 0, 0, 3, 3), {R1, R2, R3}, EMPTY},
                    102:     {"shladd",  A, OpX2aVeX4 (8, 0, 0, 4), {R1, R2, CNT2a, R3}, EMPTY},
                    103:     {"shladdp4", A, OpX2aVeX4 (8, 0, 0, 6), {R1, R2, CNT2a, R3}, EMPTY},
                    104:     {"sub",     A, OpX2aVeX4X2b (8, 0, 0, 9, 1), {R1, IMM8, R3}, EMPTY},
                    105:     {"and",     A, OpX2aVeX4X2b (8, 0, 0, 0xb, 0), {R1, IMM8, R3}, EMPTY},
                    106:     {"andcm",   A, OpX2aVeX4X2b (8, 0, 0, 0xb, 1), {R1, IMM8, R3}, EMPTY},
                    107:     {"or",      A, OpX2aVeX4X2b (8, 0, 0, 0xb, 2), {R1, IMM8, R3}, EMPTY},
                    108:     {"xor",     A, OpX2aVeX4X2b (8, 0, 0, 0xb, 3), {R1, IMM8, R3}, EMPTY},
                    109:     {"mov",     A, OpX2aVeImm14 (8, 2, 0, 0), {R1, R3}, EMPTY},
                    110:     /* A mov immediate pseudo for adds was deleted.  It failed for immediate
                    111:        operands requiring relocs, e.g. @pltoff(a).  */
                    112:     {"adds",    A, OpX2aVe (8, 2, 0), {R1, IMM14, R3}, EMPTY},
                    113:     {"addp4",   A, OpX2aVe (8, 3, 0), {R1, IMM14, R3}, EMPTY},
                    114:     {"padd1",           A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 0), {R1, R2, R3}, EMPTY},
                    115:     {"padd2",           A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 0), {R1, R2, R3}, EMPTY},
                    116:     {"padd4",           A, OpX2aZaZbX4X2b (8, 1, 1, 0, 0, 0), {R1, R2, R3}, EMPTY},
                    117:     {"padd1.sss",       A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
                    118:     {"padd2.sss",       A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 1), {R1, R2, R3}, EMPTY},
                    119:     {"padd1.uuu",       A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 2), {R1, R2, R3}, EMPTY},
                    120:     {"padd2.uuu",       A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 2), {R1, R2, R3}, EMPTY},
                    121:     {"padd1.uus",       A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 3), {R1, R2, R3}, EMPTY},
                    122:     {"padd2.uus",       A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 3), {R1, R2, R3}, EMPTY},
                    123:     {"psub1",           A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 0), {R1, R2, R3}, EMPTY},
                    124:     {"psub2",           A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 0), {R1, R2, R3}, EMPTY},
                    125:     {"psub4",           A, OpX2aZaZbX4X2b (8, 1, 1, 0, 1, 0), {R1, R2, R3}, EMPTY},
                    126:     {"psub1.sss",       A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 1), {R1, R2, R3}, EMPTY},
                    127:     {"psub2.sss",       A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 1), {R1, R2, R3}, EMPTY},
                    128:     {"psub1.uuu",       A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 2), {R1, R2, R3}, EMPTY},
                    129:     {"psub2.uuu",       A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 2), {R1, R2, R3}, EMPTY},
                    130:     {"psub1.uus",       A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 3), {R1, R2, R3}, EMPTY},
                    131:     {"psub2.uus",       A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 3), {R1, R2, R3}, EMPTY},
                    132:     {"pavg1",           A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 2), {R1, R2, R3}, EMPTY},
                    133:     {"pavg2",           A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 2), {R1, R2, R3}, EMPTY},
                    134:     {"pavg1.raz",       A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 3), {R1, R2, R3}, EMPTY},
                    135:     {"pavg2.raz",       A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 3), {R1, R2, R3}, EMPTY},
                    136:     {"pavgsub1",        A, OpX2aZaZbX4X2b (8, 1, 0, 0, 3, 2), {R1, R2, R3}, EMPTY},
                    137:     {"pavgsub2",        A, OpX2aZaZbX4X2b (8, 1, 0, 1, 3, 2), {R1, R2, R3}, EMPTY},
                    138:     {"pcmp1.eq",        A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 0), {R1, R2, R3}, EMPTY},
                    139:     {"pcmp2.eq",        A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 0), {R1, R2, R3}, EMPTY},
                    140:     {"pcmp4.eq",        A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 0), {R1, R2, R3}, EMPTY},
                    141:     {"pcmp1.gt",        A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 1), {R1, R2, R3}, EMPTY},
                    142:     {"pcmp2.gt",        A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 1), {R1, R2, R3}, EMPTY},
                    143:     {"pcmp4.gt",        A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 1), {R1, R2, R3}, EMPTY},
                    144:     {"pshladd2",        A, OpX2aZaZbX4 (8, 1, 0, 1, 4), {R1, R2, CNT2b, R3}, EMPTY},
                    145:     {"pshradd2",        A, OpX2aZaZbX4 (8, 1, 0, 1, 6), {R1, R2, CNT2b, R3}, EMPTY},
                    146:
                    147:     {"mov",             A, OpR3b (9, 0), {R1, IMM22}, PSEUDO, 0, NULL},
                    148:     {"addl",            A, Op    (9),    {R1, IMM22, R3_2}, EMPTY},
                    149:
                    150:     {"cmp.lt",          A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY},
                    151:     {"cmp.le",          A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}, EMPTY},
                    152:     {"cmp.gt",          A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}, EMPTY},
                    153:     {"cmp.ge",          A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY},
                    154:     {"cmp.lt.unc",      A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY},
                    155:     {"cmp.le.unc",      A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}, EMPTY},
                    156:     {"cmp.gt.unc",      A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}, EMPTY},
                    157:     {"cmp.ge.unc",      A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY},
                    158:     {"cmp.eq.and",      A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY},
                    159:     {"cmp.ne.andcm",    A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL},
                    160:     {"cmp.ne.and",      A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, EMPTY},
                    161:     {"cmp.eq.andcm",    A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL},
                    162:     {"cmp4.lt",                 A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R2, R3}, EMPTY},
                    163:     {"cmp4.le",                 A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R3, R2}, EMPTY},
                    164:     {"cmp4.gt",                 A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R3, R2}, EMPTY},
                    165:     {"cmp4.ge",                 A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R2, R3}, EMPTY},
                    166:     {"cmp4.lt.unc",     A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R2, R3}, EMPTY},
                    167:     {"cmp4.le.unc",     A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R3, R2}, EMPTY},
                    168:     {"cmp4.gt.unc",     A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R3, R2}, EMPTY},
                    169:     {"cmp4.ge.unc",     A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R2, R3}, EMPTY},
                    170:     {"cmp4.eq.and",     A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, EMPTY},
                    171:     {"cmp4.ne.andcm",   A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL},
                    172:     {"cmp4.ne.and",     A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, EMPTY},
                    173:     {"cmp4.eq.andcm",   A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL},
                    174:     {"cmp.gt.and",      A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY},
                    175:     {"cmp.lt.and",      A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    176:     {"cmp.le.andcm",    A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
                    177:     {"cmp.ge.andcm",    A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    178:     {"cmp.le.and",      A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY},
                    179:     {"cmp.ge.and",      A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    180:     {"cmp.gt.andcm",    A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
                    181:     {"cmp.lt.andcm",    A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    182:     {"cmp.ge.and",      A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY},
                    183:     {"cmp.le.and",      A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    184:     {"cmp.lt.andcm",    A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
                    185:     {"cmp.gt.andcm",    A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    186:     {"cmp.lt.and",      A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY},
                    187:     {"cmp.gt.and",      A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    188:     {"cmp.ge.andcm",    A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
                    189:     {"cmp.le.andcm",    A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    190:     {"cmp4.gt.and",     A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY},
                    191:     {"cmp4.lt.and",     A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    192:     {"cmp4.le.andcm",   A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
                    193:     {"cmp4.ge.andcm",   A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    194:     {"cmp4.le.and",     A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY},
                    195:     {"cmp4.ge.and",     A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    196:     {"cmp4.gt.andcm",   A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
                    197:     {"cmp4.lt.andcm",   A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    198:     {"cmp4.ge.and",     A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY},
                    199:     {"cmp4.le.and",     A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    200:     {"cmp4.lt.andcm",   A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
                    201:     {"cmp4.gt.andcm",   A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    202:     {"cmp4.lt.and",     A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY},
                    203:     {"cmp4.gt.and",     A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    204:     {"cmp4.ge.andcm",   A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
                    205:     {"cmp4.le.andcm",   A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    206:     {"cmp.lt",          A2, OpX2TaC   (0xc, 2, 0, 0), {P1, P2, IMM8, R3}, EMPTY},
                    207:     {"cmp.le",          A2, OpX2TaC   (0xc, 2, 0, 0), {P1, P2, IMM8M1, R3}, EMPTY},
                    208:     {"cmp.gt",          A2, OpX2TaC   (0xc, 2, 0, 0), {P2, P1, IMM8M1, R3}, EMPTY},
                    209:     {"cmp.ge",          A2, OpX2TaC   (0xc, 2, 0, 0), {P2, P1, IMM8, R3}, EMPTY},
                    210:     {"cmp.lt.unc",      A2, OpX2TaC   (0xc, 2, 0, 1), {P1, P2, IMM8, R3}, EMPTY},
                    211:     {"cmp.le.unc",      A2, OpX2TaC   (0xc, 2, 0, 1), {P1, P2, IMM8M1, R3}, EMPTY},
                    212:     {"cmp.gt.unc",      A2, OpX2TaC   (0xc, 2, 0, 1), {P2, P1, IMM8M1, R3}, EMPTY},
                    213:     {"cmp.ge.unc",      A2, OpX2TaC   (0xc, 2, 0, 1), {P2, P1, IMM8, R3}, EMPTY},
                    214:     {"cmp.eq.and",      A2, OpX2TaC   (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, EMPTY},
                    215:     {"cmp.ne.andcm",    A2, OpX2TaC   (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL},
                    216:     {"cmp.ne.and",      A2, OpX2TaC   (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, EMPTY},
                    217:     {"cmp.eq.andcm",    A2, OpX2TaC   (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL},
                    218:     {"cmp4.lt",                 A2, OpX2TaC   (0xc, 3, 0, 0), {P1, P2, IMM8, R3}, EMPTY},
                    219:     {"cmp4.le",                 A2, OpX2TaC   (0xc, 3, 0, 0), {P1, P2, IMM8M1, R3}, EMPTY},
                    220:     {"cmp4.gt",                 A2, OpX2TaC   (0xc, 3, 0, 0), {P2, P1, IMM8M1, R3}, EMPTY},
                    221:     {"cmp4.ge",                 A2, OpX2TaC   (0xc, 3, 0, 0), {P2, P1, IMM8, R3}, EMPTY},
                    222:     {"cmp4.lt.unc",     A2, OpX2TaC   (0xc, 3, 0, 1), {P1, P2, IMM8, R3}, EMPTY},
                    223:     {"cmp4.le.unc",     A2, OpX2TaC   (0xc, 3, 0, 1), {P1, P2, IMM8M1, R3}, EMPTY},
                    224:     {"cmp4.gt.unc",     A2, OpX2TaC   (0xc, 3, 0, 1), {P2, P1, IMM8M1, R3}, EMPTY},
                    225:     {"cmp4.ge.unc",     A2, OpX2TaC   (0xc, 3, 0, 1), {P2, P1, IMM8, R3}, EMPTY},
                    226:     {"cmp4.eq.and",     A2, OpX2TaC   (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, EMPTY},
                    227:     {"cmp4.ne.andcm",   A2, OpX2TaC   (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL},
                    228:     {"cmp4.ne.and",     A2, OpX2TaC   (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, EMPTY},
                    229:     {"cmp4.eq.andcm",   A2, OpX2TaC   (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL},
                    230:     {"cmp.ltu",                 A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY},
                    231:     {"cmp.leu",                 A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R3, R2}, EMPTY},
                    232:     {"cmp.gtu",                 A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R3, R2}, EMPTY},
                    233:     {"cmp.geu",                 A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY},
                    234:     {"cmp.ltu.unc",     A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY},
                    235:     {"cmp.leu.unc",     A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R3, R2}, EMPTY},
                    236:     {"cmp.gtu.unc",     A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R3, R2}, EMPTY},
                    237:     {"cmp.geu.unc",     A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY},
                    238:     {"cmp.eq.or",       A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY},
                    239:     {"cmp.ne.orcm",     A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL},
                    240:     {"cmp.ne.or",       A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, EMPTY},
                    241:     {"cmp.eq.orcm",     A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL},
                    242:     {"cmp4.ltu",        A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R2, R3}, EMPTY},
                    243:     {"cmp4.leu",        A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R3, R2}, EMPTY},
                    244:     {"cmp4.gtu",        A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R3, R2}, EMPTY},
                    245:     {"cmp4.geu",        A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R2, R3}, EMPTY},
                    246:     {"cmp4.ltu.unc",    A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R2, R3}, EMPTY},
                    247:     {"cmp4.leu.unc",    A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R3, R2}, EMPTY},
                    248:     {"cmp4.gtu.unc",    A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R3, R2}, EMPTY},
                    249:     {"cmp4.geu.unc",    A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R2, R3}, EMPTY},
                    250:     {"cmp4.eq.or",      A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, EMPTY},
                    251:     {"cmp4.ne.orcm",    A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL},
                    252:     {"cmp4.ne.or",      A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, EMPTY},
                    253:     {"cmp4.eq.orcm",    A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL},
                    254:     {"cmp.gt.or",       A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY},
                    255:     {"cmp.lt.or",       A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    256:     {"cmp.le.orcm",     A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
                    257:     {"cmp.ge.orcm",     A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    258:     {"cmp.le.or",       A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY},
                    259:     {"cmp.ge.or",       A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    260:     {"cmp.gt.orcm",     A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
                    261:     {"cmp.lt.orcm",     A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    262:     {"cmp.ge.or",       A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY},
                    263:     {"cmp.le.or",       A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    264:     {"cmp.lt.orcm",     A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
                    265:     {"cmp.gt.orcm",     A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    266:     {"cmp.lt.or",       A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY},
                    267:     {"cmp.gt.or",       A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    268:     {"cmp.ge.orcm",     A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
                    269:     {"cmp.le.orcm",     A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    270:     {"cmp4.gt.or",      A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY},
                    271:     {"cmp4.lt.or",      A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    272:     {"cmp4.le.orcm",    A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
                    273:     {"cmp4.ge.orcm",    A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    274:     {"cmp4.le.or",      A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY},
                    275:     {"cmp4.ge.or",      A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    276:     {"cmp4.gt.orcm",    A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
                    277:     {"cmp4.lt.orcm",    A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    278:     {"cmp4.ge.or",      A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY},
                    279:     {"cmp4.le.or",      A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    280:     {"cmp4.lt.orcm",    A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
                    281:     {"cmp4.gt.orcm",    A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    282:     {"cmp4.lt.or",      A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY},
                    283:     {"cmp4.gt.or",      A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    284:     {"cmp4.ge.orcm",    A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL},
                    285:     {"cmp4.le.orcm",    A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    286:     {"cmp.ltu",                 A2, OpX2TaC   (0xd, 2, 0, 0), {P1, P2, IMM8, R3}, EMPTY},
                    287:     {"cmp.leu",                 A2, OpX2TaC   (0xd, 2, 0, 0), {P1, P2, IMM8M1U8, R3}, EMPTY},
                    288:     {"cmp.gtu",                 A2, OpX2TaC   (0xd, 2, 0, 0), {P2, P1, IMM8M1U8, R3}, EMPTY},
                    289:     {"cmp.geu",                 A2, OpX2TaC   (0xd, 2, 0, 0), {P2, P1, IMM8, R3}, EMPTY},
                    290:     {"cmp.ltu.unc",     A2, OpX2TaC   (0xd, 2, 0, 1), {P1, P2, IMM8, R3}, EMPTY},
                    291:     {"cmp.leu.unc",     A2, OpX2TaC   (0xd, 2, 0, 1), {P1, P2, IMM8M1U8, R3}, EMPTY},
                    292:     {"cmp.gtu.unc",     A2, OpX2TaC   (0xd, 2, 0, 1), {P2, P1, IMM8M1U8, R3}, EMPTY},
                    293:     {"cmp.geu.unc",     A2, OpX2TaC   (0xd, 2, 0, 1), {P2, P1, IMM8, R3}, EMPTY},
                    294:     {"cmp.eq.or",       A2, OpX2TaC   (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, EMPTY},
                    295:     {"cmp.ne.orcm",     A2, OpX2TaC   (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL},
                    296:     {"cmp.ne.or",       A2, OpX2TaC   (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, EMPTY},
                    297:     {"cmp.eq.orcm",     A2, OpX2TaC   (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL},
                    298:     {"cmp4.ltu",        A2, OpX2TaC   (0xd, 3, 0, 0), {P1, P2, IMM8U4, R3}, EMPTY},
                    299:     {"cmp4.leu",        A2, OpX2TaC   (0xd, 3, 0, 0), {P1, P2, IMM8M1U4, R3}, EMPTY},
                    300:     {"cmp4.gtu",        A2, OpX2TaC   (0xd, 3, 0, 0), {P2, P1, IMM8M1U4, R3}, EMPTY},
                    301:     {"cmp4.geu",        A2, OpX2TaC   (0xd, 3, 0, 0), {P2, P1, IMM8U4, R3}, EMPTY},
                    302:     {"cmp4.ltu.unc",    A2, OpX2TaC   (0xd, 3, 0, 1), {P1, P2, IMM8U4, R3}, EMPTY},
                    303:     {"cmp4.leu.unc",    A2, OpX2TaC   (0xd, 3, 0, 1), {P1, P2, IMM8M1U4, R3}, EMPTY},
                    304:     {"cmp4.gtu.unc",    A2, OpX2TaC   (0xd, 3, 0, 1), {P2, P1, IMM8M1U4, R3}, EMPTY},
                    305:     {"cmp4.geu.unc",    A2, OpX2TaC   (0xd, 3, 0, 1), {P2, P1, IMM8U4, R3}, EMPTY},
                    306:     {"cmp4.eq.or",      A2, OpX2TaC   (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, EMPTY},
                    307:     {"cmp4.ne.orcm",    A2, OpX2TaC   (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL},
                    308:     {"cmp4.ne.or",      A2, OpX2TaC   (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, EMPTY},
                    309:     {"cmp4.eq.orcm",    A2, OpX2TaC   (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL},
                    310:     {"cmp.eq",          A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY},
                    311:     {"cmp.ne",          A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY},
                    312:     {"cmp.eq.unc",      A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY},
                    313:     {"cmp.ne.unc",      A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY},
                    314:     {"cmp.eq.or.andcm",         A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY},
                    315:     {"cmp.ne.and.orcm",         A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO, 0, NULL},
                    316:     {"cmp.ne.or.andcm",         A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P1, P2, R2, R3}, EMPTY},
                    317:     {"cmp.eq.and.orcm",         A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO, 0, NULL},
                    318:     {"cmp4.eq",                 A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P1, P2, R2, R3}, EMPTY},
                    319:     {"cmp4.ne",                 A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P2, P1, R2, R3}, EMPTY},
                    320:     {"cmp4.eq.unc",     A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P1, P2, R2, R3}, EMPTY},
                    321:     {"cmp4.ne.unc",     A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P2, P1, R2, R3}, EMPTY},
                    322:     {"cmp4.eq.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P1, P2, R2, R3}, EMPTY},
                    323:     {"cmp4.ne.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO, 0, NULL},
                    324:     {"cmp4.ne.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P1, P2, R2, R3}, EMPTY},
                    325:     {"cmp4.eq.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO, 0, NULL},
                    326:     {"cmp.gt.or.andcm",         A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY},
                    327:     {"cmp.lt.or.andcm",         A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    328:     {"cmp.le.and.orcm",         A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL},
                    329:     {"cmp.ge.and.orcm",         A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL},
                    330:     {"cmp.le.or.andcm",         A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY},
                    331:     {"cmp.ge.or.andcm",         A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    332:     {"cmp.gt.and.orcm",         A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL},
                    333:     {"cmp.lt.and.orcm",         A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL},
                    334:     {"cmp.ge.or.andcm",         A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY},
                    335:     {"cmp.le.or.andcm",         A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    336:     {"cmp.lt.and.orcm",         A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL},
                    337:     {"cmp.gt.and.orcm",         A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL},
                    338:     {"cmp.lt.or.andcm",         A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY},
                    339:     {"cmp.gt.or.andcm",         A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    340:     {"cmp.ge.and.orcm",         A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL},
                    341:     {"cmp.le.and.orcm",         A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL},
                    342:     {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY},
                    343:     {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    344:     {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL},
                    345:     {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL},
                    346:     {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY},
                    347:     {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    348:     {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL},
                    349:     {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL},
                    350:     {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY},
                    351:     {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    352:     {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL},
                    353:     {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL},
                    354:     {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY},
                    355:     {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL},
                    356:     {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL},
                    357:     {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL},
                    358:     {"cmp.eq",          A2, OpX2TaC   (0xe, 2, 0, 0), {P1, P2, IMM8, R3}, EMPTY},
                    359:     {"cmp.ne",          A2, OpX2TaC   (0xe, 2, 0, 0), {P2, P1, IMM8, R3}, EMPTY},
                    360:     {"cmp.eq.unc",      A2, OpX2TaC   (0xe, 2, 0, 1), {P1, P2, IMM8, R3}, EMPTY},
                    361:     {"cmp.ne.unc",      A2, OpX2TaC   (0xe, 2, 0, 1), {P2, P1, IMM8, R3}, EMPTY},
                    362:     {"cmp.eq.or.andcm",         A2, OpX2TaC   (0xe, 2, 1, 0), {P1, P2, IMM8, R3}, EMPTY},
                    363:     {"cmp.ne.and.orcm",         A2, OpX2TaC   (0xe, 2, 1, 0), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL},
                    364:     {"cmp.ne.or.andcm",         A2, OpX2TaC   (0xe, 2, 1, 1), {P1, P2, IMM8, R3}, EMPTY},
                    365:     {"cmp.eq.and.orcm",         A2, OpX2TaC   (0xe, 2, 1, 1), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL},
                    366:     {"cmp4.eq",                 A2, OpX2TaC   (0xe, 3, 0, 0), {P1, P2, IMM8, R3}, EMPTY},
                    367:     {"cmp4.ne",                 A2, OpX2TaC   (0xe, 3, 0, 0), {P2, P1, IMM8, R3}, EMPTY},
                    368:     {"cmp4.eq.unc",     A2, OpX2TaC   (0xe, 3, 0, 1), {P1, P2, IMM8, R3}, EMPTY},
                    369:     {"cmp4.ne.unc",     A2, OpX2TaC   (0xe, 3, 0, 1), {P2, P1, IMM8, R3}, EMPTY},
                    370:     {"cmp4.eq.or.andcm", A2, OpX2TaC   (0xe, 3, 1, 0), {P1, P2, IMM8, R3}, EMPTY},
                    371:     {"cmp4.ne.and.orcm", A2, OpX2TaC   (0xe, 3, 1, 0), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL},
                    372:     {"cmp4.ne.or.andcm", A2, OpX2TaC   (0xe, 3, 1, 1), {P1, P2, IMM8, R3}, EMPTY},
                    373:     {"cmp4.eq.and.orcm", A2, OpX2TaC   (0xe, 3, 1, 1), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL},
                    374:
                    375:     {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL}
                    376:   };
                    377:
                    378: #undef A
                    379: #undef A2
                    380: #undef bC
                    381: #undef bImm14
                    382: #undef bR3a
                    383: #undef bR3b
                    384: #undef bTa
                    385: #undef bTb
                    386: #undef bVe
                    387: #undef bX
                    388: #undef bX2
                    389: #undef bX2a
                    390: #undef bX2b
                    391: #undef bX4
                    392: #undef bZa
                    393: #undef bZb
                    394: #undef mC
                    395: #undef mImm14
                    396: #undef mR3a
                    397: #undef mR3b
                    398: #undef mTa
                    399: #undef mTb
                    400: #undef mVe
                    401: #undef mX
                    402: #undef mX2
                    403: #undef mX2a
                    404: #undef mX2b
                    405: #undef mX4
                    406: #undef mZa
                    407: #undef mZb
                    408: #undef OpR3a
                    409: #undef OpR3b
                    410: #undef OpX2aVe
                    411: #undef OpX2aVeImm14
                    412: #undef OpX2aVeX4
                    413: #undef OpX2aVeX4X2b
                    414: #undef OpX2TbTaC
                    415: #undef OpX2TaC
                    416: #undef OpX2aZaZbX4
                    417: #undef OpX2aZaZbX4X2b
                    418: #undef EMPTY

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