Annotation of src/external/gpl3/binutils.old/dist/opcodes/d10v-opc.c, Revision 1.1.1.2
1.1 christos 1: /* d10v-opc.c -- D10V opcode list
1.1.1.2 ! christos 2: Copyright (C) 1996-2015 Free Software Foundation, Inc.
1.1 christos 3: Written by Martin Hunt, Cygnus Support
4:
5: This file is part of the GNU opcodes library.
6:
7: This library is free software; you can redistribute it and/or modify
8: it under the terms of the GNU General Public License as published by
9: the Free Software Foundation; either version 3, or (at your option)
10: any later version.
11:
12: It is distributed in the hope that it will be useful, but WITHOUT
13: ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14: or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15: License for more details.
16:
17: You should have received a copy of the GNU General Public License
18: along with this file; see the file COPYING. If not, write to the Free
19: Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20: MA 02110-1301, USA. */
21:
22: #include "sysdep.h"
23: #include <stdio.h>
24: #include "opcode/d10v.h"
25:
26:
27: /* The table is sorted. Suitable for searching by a binary search. */
28: const struct pd_reg d10v_predefined_registers[] =
29: {
30: { "a0", NULL, OPERAND_ACC0+0 },
31: { "a1", NULL, OPERAND_ACC1+1 },
32: { "bpc", NULL, OPERAND_CONTROL+3 },
33: { "bpsw", NULL, OPERAND_CONTROL+1 },
34: { "c", NULL, OPERAND_CFLAG+3 },
35: { "cr0", "psw", OPERAND_CONTROL },
36: { "cr1", "bpsw", OPERAND_CONTROL+1 },
37: { "cr10", "mod_s", OPERAND_CONTROL+10 },
38: { "cr11", "mod_e", OPERAND_CONTROL+11 },
39: { "cr12", NULL, OPERAND_CONTROL+12 },
40: { "cr13", NULL, OPERAND_CONTROL+13 },
41: { "cr14", "iba", OPERAND_CONTROL+14 },
42: { "cr15", NULL, OPERAND_CONTROL+15 },
43: { "cr2", "pc", OPERAND_CONTROL+2 },
44: { "cr3", "bpc", OPERAND_CONTROL+3 },
45: { "cr4", "dpsw", OPERAND_CONTROL+4 },
46: { "cr5", "dpc", OPERAND_CONTROL+5 },
47: { "cr6", NULL, OPERAND_CONTROL+6 },
48: { "cr7", "rpt_c", OPERAND_CONTROL+7 },
49: { "cr8", "rpt_s", OPERAND_CONTROL+8 },
50: { "cr9", "rpt_e", OPERAND_CONTROL+9 },
51: { "dpc", NULL, OPERAND_CONTROL+5 },
52: { "dpsw", NULL, OPERAND_CONTROL+4 },
53: { "f0", NULL, OPERAND_FFLAG+0 },
54: { "f1", NULL, OPERAND_FFLAG+1 },
55: { "iba", NULL, OPERAND_CONTROL+14 },
56: { "link", "r13", OPERAND_GPR+13 },
57: { "mod_e", NULL, OPERAND_CONTROL+11 },
58: { "mod_s", NULL, OPERAND_CONTROL+10 },
59: { "pc", NULL, OPERAND_CONTROL+2 },
60: { "psw", NULL, OPERAND_CONTROL+0 },
61: { "r0", NULL, OPERAND_GPR+0 },
62: { "r0-r1", NULL, OPERAND_GPR+0},
63: { "r1", NULL, OPERAND_GPR+1 },
64: { "r1", NULL, OPERAND_GPR+1 },
65: { "r10", NULL, OPERAND_GPR+10 },
66: { "r10-r11", NULL, OPERAND_GPR+10 },
67: { "r11", NULL, OPERAND_GPR+11 },
68: { "r12", NULL, OPERAND_GPR+12 },
69: { "r12-r13", NULL, OPERAND_GPR+12 },
70: { "r13", NULL, OPERAND_GPR+13 },
71: { "r14", NULL, OPERAND_GPR+14 },
72: { "r14-r15", NULL, OPERAND_GPR+14 },
73: { "r15", "sp", OPERAND_SP|(OPERAND_GPR+15) },
74: { "r2", NULL, OPERAND_GPR+2 },
75: { "r2-r3", NULL, OPERAND_GPR+2 },
76: { "r3", NULL, OPERAND_GPR+3 },
77: { "r4", NULL, OPERAND_GPR+4 },
78: { "r4-r5", NULL, OPERAND_GPR+4 },
79: { "r5", NULL, OPERAND_GPR+5 },
80: { "r6", NULL, OPERAND_GPR+6 },
81: { "r6-r7", NULL, OPERAND_GPR+6 },
82: { "r7", NULL, OPERAND_GPR+7 },
83: { "r8", NULL, OPERAND_GPR+8 },
84: { "r8-r9", NULL, OPERAND_GPR+8 },
85: { "r9", NULL, OPERAND_GPR+9 },
86: { "rpt_c", NULL, OPERAND_CONTROL+7 },
87: { "rpt_e", NULL, OPERAND_CONTROL+9 },
88: { "rpt_s", NULL, OPERAND_CONTROL+8 },
89: { "sp", NULL, OPERAND_SP|(OPERAND_GPR+15) },
90: };
91:
1.1.1.2 ! christos 92: int
! 93: d10v_reg_name_cnt (void)
1.1 christos 94: {
95: return (sizeof(d10v_predefined_registers) / sizeof(struct pd_reg));
96: }
97:
98: const struct d10v_operand d10v_operands[] =
99: {
100: #define UNUSED (0)
101: { 0, 0, 0 },
102: #define RSRC (UNUSED + 1)
103: { 4, 1, OPERAND_GPR|OPERAND_REG },
104: #define RSRC_SP (RSRC + 1)
105: { 4, 1, OPERAND_SP|OPERAND_GPR|OPERAND_REG },
106: #define RSRC_NOSP (RSRC_SP + 1)
107: { 4, 1, OPERAND_NOSP|OPERAND_GPR|OPERAND_REG },
108: #define RDST (RSRC_NOSP + 1)
109: { 4, 5, OPERAND_DEST|OPERAND_GPR|OPERAND_REG },
110: #define ASRC (RDST + 1)
111: { 1, 4, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG },
112: #define ASRC0ONLY (ASRC + 1)
113: { 1, 4, OPERAND_ACC0|OPERAND_REG },
114: #define ADST (ASRC0ONLY + 1)
115: { 1, 8, OPERAND_DEST|OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG },
116: #define RSRCE (ADST + 1)
117: { 4, 1, OPERAND_EVEN|OPERAND_GPR|OPERAND_REG },
118: #define RDSTE (RSRCE + 1)
119: { 4, 5, OPERAND_EVEN|OPERAND_DEST|OPERAND_GPR|OPERAND_REG },
120: #define NUM16 (RDSTE + 1)
121: { 16, 0, OPERAND_NUM|OPERAND_SIGNED },
122: #define NUM3 (NUM16 + 1) /* rac, rachi */
123: { 3, 1, OPERAND_NUM|OPERAND_SIGNED|RESTRICTED_NUM3 },
124: #define NUM4 (NUM3 + 1)
125: { 4, 1, OPERAND_NUM|OPERAND_SIGNED },
126: #define UNUM4 (NUM4 + 1)
127: { 4, 1, OPERAND_NUM },
128: #define UNUM4S (UNUM4 + 1) /* addi, slli, srai, srli, subi */
129: { 4, 1, OPERAND_NUM|OPERAND_SHIFT },
130: #define UNUM8 (UNUM4S + 1) /* repi */
131: { 8, 16, OPERAND_NUM },
132: #define UNUM16 (UNUM8 + 1) /* cmpui */
133: { 16, 0, OPERAND_NUM },
134: #define ANUM16 (UNUM16 + 1)
135: { 16, 0, OPERAND_ADDR|OPERAND_SIGNED },
136: #define ANUM8 (ANUM16 + 1)
137: { 8, 0, OPERAND_ADDR|OPERAND_SIGNED },
138: #define ASRC2 (ANUM8 + 1)
139: { 1, 8, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG },
140: #define RSRC2 (ASRC2 + 1)
141: { 4, 5, OPERAND_GPR|OPERAND_REG },
142: #define RSRC2E (RSRC2 + 1)
143: { 4, 5, OPERAND_GPR|OPERAND_REG|OPERAND_EVEN },
144: #define ASRC0 (RSRC2E + 1)
145: { 1, 0, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG },
146: #define ADST0 (ASRC0 + 1)
147: { 1, 0, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG|OPERAND_DEST },
148: #define FFSRC (ADST0 + 1)
149: { 2, 1, OPERAND_REG | OPERAND_FFLAG },
150: #define CFSRC (FFSRC + 1)
151: { 2, 1, OPERAND_REG | OPERAND_CFLAG },
152: #define FDST (CFSRC + 1)
153: { 1, 5, OPERAND_REG | OPERAND_FFLAG | OPERAND_DEST},
154: #define ATSIGN (FDST + 1)
155: { 0, 0, OPERAND_ATSIGN},
156: #define ATPAR (ATSIGN + 1) /* "@(" */
157: { 0, 0, OPERAND_ATPAR},
158: #define PLUS (ATPAR + 1) /* postincrement */
159: { 0, 0, OPERAND_PLUS},
160: #define MINUS (PLUS + 1) /* postdecrement */
161: { 0, 0, OPERAND_MINUS},
162: #define ATMINUS (MINUS + 1) /* predecrement */
163: { 0, 0, OPERAND_ATMINUS},
164: #define CSRC (ATMINUS + 1) /* control register */
165: { 4, 1, OPERAND_REG|OPERAND_CONTROL},
166: #define CDST (CSRC + 1) /* control register */
167: { 4, 5, OPERAND_REG|OPERAND_CONTROL|OPERAND_DEST},
168: };
169:
170: const struct d10v_opcode d10v_opcodes[] = {
171: { "abs", SHORT_2, 1, EITHER, PAR|WF0, 0x4607, 0x7e1f, { RDST } },
172: { "abs", SHORT_2, 1, IU, PAR|WF0, 0x5607, 0x7eff, { ADST } },
173: { "add", SHORT_2, 1, EITHER, PAR|WCAR, 0x0200, 0x7e01, { RDST, RSRC } },
174: { "add", SHORT_2, 1, IU, PAR, 0x1201, 0x7ee3, { ADST, RSRCE } },
175: { "add", SHORT_2, 1, IU, PAR, 0x1203, 0x7eef, { ADST, ASRC } },
176: { "add2w", SHORT_2, 2, IU, PAR|WCAR, 0x1200, 0x7e23, { RDSTE, RSRCE } },
177: { "add3", LONG_L, 1, MU, SEQ|WCAR, 0x1000000, 0x3f000000, { RDST, RSRC, NUM16 } },
178: { "addac3", LONG_R, 1, IU, SEQ, 0x17000200, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } },
179: { "addac3", LONG_R, 1, IU, SEQ, 0x17000202, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } },
180: { "addac3s", LONG_R, 1, IU, SEQ, 0x17001200, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } },
181: { "addac3s", LONG_R, 1, IU, SEQ, 0x17001202, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } },
182: { "addi", SHORT_2, 1, EITHER, PAR|WCAR, 0x201, 0x7e01, { RDST, UNUM4S } },
183: { "and", SHORT_2, 1, EITHER, PAR, 0xc00, 0x7e01, { RDST, RSRC } },
184: { "and3", LONG_L, 1, MU, SEQ, 0x6000000, 0x3f000000, { RDST, RSRC, NUM16 } },
185: { "bclri", SHORT_2, 1, IU, PAR, 0xc01, 0x7e01, { RDST, UNUM4 } },
186: { "bl", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } },
187: { "bl.s", SHORT_B, 3, MU, ALONE|BRANCH_LINK|PAR, 0x4900, 0x7f00, { ANUM8 } },
188: { "bl.l", LONG_B, 3, MU, BRANCH_LINK|SEQ, 0x24800000, 0x3fff0000, { ANUM16 } },
189: { "bnoti", SHORT_2, 1, IU, PAR, 0xa01, 0x7e01, { RDST, UNUM4 } },
190: { "bra", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } },
191: { "bra.s", SHORT_B, 3, MU, ALONE|BRANCH|PAR, 0x4800, 0x7f00, { ANUM8 } },
192: { "bra.l", LONG_B, 3, MU, BRANCH|SEQ, 0x24000000, 0x3fff0000, { ANUM16 } },
193: { "brf0f", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } },
194: { "brf0f.s", SHORT_B, 3, MU, BRANCH|PAR|RF0, 0x4a00, 0x7f00, { ANUM8 } },
195: { "brf0f.l", LONG_B, 3, MU, SEQ, 0x25000000, 0x3fff0000, { ANUM16 } },
196: { "brf0t", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } },
197: { "brf0t.s", SHORT_B, 3, MU, BRANCH|PAR|RF0, 0x4b00, 0x7f00, { ANUM8 } },
198: { "brf0t.l", LONG_B, 3, MU, SEQ, 0x25800000, 0x3fff0000, { ANUM16 } },
199: { "bseti", SHORT_2, 1, IU, PAR, 0x801, 0x7e01, { RDST, UNUM4 } },
200: { "btsti", SHORT_2, 1, IU, PAR|WF0, 0xe01, 0x7e01, { RSRC2, UNUM4 } },
201: { "clrac", SHORT_2, 1, IU, PAR, 0x5601, 0x7eff, { ADST } },
202: { "cmp", SHORT_2, 1, EITHER, PAR|WF0, 0x600, 0x7e01, { RSRC2, RSRC } },
203: { "cmp", SHORT_2, 1, IU, PAR|WF0, 0x1603, 0x7eef, { ASRC2, ASRC } },
204: { "cmpeq", SHORT_2, 1, EITHER, PAR|WF0, 0x400, 0x7e01, { RSRC2, RSRC } },
205: { "cmpeq", SHORT_2, 1, IU, PAR|WF0, 0x1403, 0x7eef, { ASRC2, ASRC } },
206: { "cmpeqi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } },
207: { "cmpeqi.s", SHORT_2, 1, EITHER, PAR|WF0, 0x401, 0x7e01, { RSRC2, NUM4 } },
208: { "cmpeqi.l", LONG_L, 1, MU, SEQ, 0x2000000, 0x3f0f0000, { RSRC2, NUM16 } },
209: { "cmpi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } },
210: { "cmpi.s", SHORT_2, 1, EITHER, PAR|WF0, 0x601, 0x7e01, { RSRC2, NUM4 } },
211: { "cmpi.l", LONG_L, 1, MU, SEQ, 0x3000000, 0x3f0f0000, { RSRC2, NUM16 } },
212: { "cmpu", SHORT_2, 1, EITHER, PAR|WF0, 0x4600, 0x7e01, { RSRC2, RSRC } },
213: { "cmpui", LONG_L, 1, MU, SEQ, 0x23000000, 0x3f0f0000, { RSRC2, UNUM16 } },
214: { "cpfg", SHORT_2, 1, MU, PAR, 0x4e0f, 0x7fdf, { FDST, CFSRC } },
215: { "cpfg", SHORT_2, 1, MU, PAR, 0x4e09, 0x7fd9, { FDST, FFSRC } },
216: { "dbt", SHORT_2, 5, MU, ALONE|PAR, 0x5f20, 0x7fff, { 0 } },
217: { "divs", LONG_L, 1, BOTH, SEQ, 0x14002800, 0x3f10fe21, { RDSTE, RSRC } },
218: { "exef0f", SHORT_2, 1, EITHER, PARONLY, 0x4e04, 0x7fff, { 0 } },
219: { "exef0t", SHORT_2, 1, EITHER, PARONLY, 0x4e24, 0x7fff, { 0 } },
220: { "exef1f", SHORT_2, 1, EITHER, PARONLY, 0x4e40, 0x7fff, { 0 } },
221: { "exef1t", SHORT_2, 1, EITHER, PARONLY, 0x4e42, 0x7fff, { 0 } },
222: { "exefaf", SHORT_2, 1, EITHER, PARONLY, 0x4e00, 0x7fff, { 0 } },
223: { "exefat", SHORT_2, 1, EITHER, PARONLY, 0x4e02, 0x7fff, { 0 } },
224: { "exetaf", SHORT_2, 1, EITHER, PARONLY, 0x4e20, 0x7fff, { 0 } },
225: { "exetat", SHORT_2, 1, EITHER, PARONLY, 0x4e22, 0x7fff, { 0 } },
226: { "exp", LONG_R, 1, IU, SEQ, 0x15002a00, 0x3ffffe03, { RDST, RSRCE } },
227: { "exp", LONG_R, 1, IU, SEQ, 0x15002a02, 0x3ffffe0f, { RDST, ASRC } },
228: { "jl", SHORT_2, 3, MU, ALONE|BRANCH_LINK|PAR, 0x4d00, 0x7fe1, { RSRC } },
229: { "jmp", SHORT_2, 3, MU, ALONE|BRANCH|PAR, 0x4c00, 0x7fe1, { RSRC } },
230: { "ld", LONG_L, 1, MU, SEQ, 0x30000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } },
231: { "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6401, 0x7e01, { RDST, ATSIGN, RSRC, MINUS } },
232: { "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6001, 0x7e01, { RDST, ATSIGN, RSRC, PLUS } },
233: { "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6000, 0x7e01, { RDST, ATSIGN, RSRC } },
234: { "ld", LONG_L, 1, MU, SEQ, 0x32010000, 0x3f0f0000, { RDST, ATSIGN, NUM16 } },
235: { "ld2w", LONG_L, 1, MU, SEQ, 0x31000000, 0x3f100000, { RDSTE, ATPAR, NUM16, RSRC } },
236: { "ld2w", SHORT_2, 1, MU, PAR|RMEM, 0x6601, 0x7e21, { RDSTE, ATSIGN, RSRC, MINUS } },
237: { "ld2w", SHORT_2, 1, MU, PAR|RMEM, 0x6201, 0x7e21, { RDSTE, ATSIGN, RSRC, PLUS } },
238: { "ld2w", SHORT_2, 1, MU, PAR|RMEM, 0x6200, 0x7e21, { RDSTE, ATSIGN, RSRC } },
239: { "ld2w", LONG_L, 1, MU, SEQ, 0x33010000, 0x3f1f0000, { RDSTE, ATSIGN, NUM16 } },
240: { "ldb", LONG_L, 1, MU, SEQ, 0x38000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } },
241: { "ldb", SHORT_2, 1, MU, PAR|RMEM, 0x7000, 0x7e01, { RDST, ATSIGN, RSRC } },
242: { "ldi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } },
243: { "ldi.s", SHORT_2, 1, EITHER, PAR|RMEM, 0x4001, 0x7e01 , { RDST, NUM4 } },
244: { "ldi.l", LONG_L, 1, MU, SEQ, 0x20000000, 0x3f0f0000, { RDST, NUM16 } },
245: { "ldub", LONG_L, 1, MU, SEQ, 0x39000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } },
246: { "ldub", SHORT_2, 1, MU, PAR|RMEM, 0x7200, 0x7e01, { RDST, ATSIGN, RSRC } },
247: { "mac", SHORT_2, 1, IU, PAR, 0x2a00, 0x7e00, { ADST0, RSRC2, RSRC } },
248: { "macsu", SHORT_2, 1, IU, PAR, 0x1a00, 0x7e00, { ADST0, RSRC2, RSRC } },
249: { "macu", SHORT_2, 1, IU, PAR, 0x3a00, 0x7e00, { ADST0, RSRC2, RSRC } },
250: { "max", SHORT_2, 1, IU, PAR|WF0, 0x2600, 0x7e01, { RDST, RSRC } },
251: { "max", SHORT_2, 1, IU, PAR|WF0, 0x3600, 0x7ee3, { ADST, RSRCE } },
252: { "max", SHORT_2, 1, IU, PAR|WF0, 0x3602, 0x7eef, { ADST, ASRC } },
253: { "min", SHORT_2, 1, IU, PAR|WF0, 0x2601, 0x7e01 , { RDST, RSRC } },
254: { "min", SHORT_2, 1, IU, PAR|WF0, 0x3601, 0x7ee3 , { ADST, RSRCE } },
255: { "min", SHORT_2, 1, IU, PAR|WF0, 0x3603, 0x7eef, { ADST, ASRC } },
256: { "msb", SHORT_2, 1, IU, PAR, 0x2800, 0x7e00, { ADST0, RSRC2, RSRC } },
257: { "msbsu", SHORT_2, 1, IU, PAR, 0x1800, 0x7e00, { ADST0, RSRC2, RSRC } },
258: { "msbu", SHORT_2, 1, IU, PAR, 0x3800, 0x7e00, { ADST0, RSRC2, RSRC } },
259: { "mul", SHORT_2, 1, IU, PAR, 0x2e00, 0x7e01 , { RDST, RSRC } },
260: { "mulx", SHORT_2, 1, IU, PAR, 0x2c00, 0x7e00, { ADST0, RSRC2, RSRC } },
261: { "mulxsu", SHORT_2, 1, IU, PAR, 0x1c00, 0x7e00, { ADST0, RSRC2, RSRC } },
262: { "mulxu", SHORT_2, 1, IU, PAR, 0x3c00, 0x7e00, { ADST0, RSRC2, RSRC } },
263: { "mv", SHORT_2, 1, EITHER, PAR, 0x4000, 0x7e01, { RDST, RSRC } },
264: { "mv2w", SHORT_2, 1, IU, PAR, 0x5000, 0x7e23, { RDSTE, RSRCE } },
265: { "mv2wfac", SHORT_2, 1, IU, PAR, 0x3e00, 0x7e2f, { RDSTE, ASRC } },
266: { "mv2wtac", SHORT_2, 1, IU, PAR, 0x3e01, 0x7ee3, { RSRCE, ADST } },
267: { "mvac", SHORT_2, 1, IU, PAR, 0x3e03, 0x7eef, { ADST, ASRC } },
268: { "mvb", SHORT_2, 1, IU, PAR, 0x5400, 0x7e01, { RDST, RSRC } },
269: { "mvf0f", SHORT_2, 1, EITHER, PAR|RF0, 0x4400, 0x7e01, { RDST, RSRC } },
270: { "mvf0t", SHORT_2, 1, EITHER, PAR|RF0, 0x4401, 0x7e01, { RDST, RSRC } },
271: { "mvfacg", SHORT_2, 1, IU, PAR, 0x1e04, 0x7e0f, { RDST, ASRC } },
272: { "mvfachi", SHORT_2, 1, IU, PAR, 0x1e00, 0x7e0f, { RDST, ASRC } },
273: { "mvfaclo", SHORT_2, 1, IU, PAR, 0x1e02, 0x7e0f, { RDST, ASRC } },
274: { "mvfc", SHORT_2, 1, MU, PAR, 0x5200, 0x7e01, { RDST, CSRC } },
275: { "mvtacg", SHORT_2, 1, IU, PAR, 0x1e41, 0x7ee1, { RSRC, ADST } },
276: { "mvtachi", SHORT_2, 1, IU, PAR, 0x1e01, 0x7ee1, { RSRC, ADST } },
277: { "mvtaclo", SHORT_2, 1, IU, PAR, 0x1e21, 0x7ee1, { RSRC, ADST } },
278: { "mvtc", SHORT_2, 1, MU, PAR, 0x5600, 0x7e01, { RSRC, CDST } },
279: { "mvub", SHORT_2, 1, IU, PAR, 0x5401, 0x7e01, { RDST, RSRC } },
280: { "neg", SHORT_2, 1, EITHER, PAR, 0x4605, 0x7e1f, { RDST } },
281: { "neg", SHORT_2, 1, IU, PAR, 0x5605, 0x7eff, { ADST } },
282: { "nop", SHORT_2, 1, EITHER, PAR, 0x5e00, 0x7fff, { 0 } },
283: { "not", SHORT_2, 1, EITHER, PAR, 0x4603, 0x7e1f, { RDST } },
284: { "or", SHORT_2, 1, EITHER, PAR, 0x800, 0x7e01, { RDST, RSRC } },
285: { "or3", LONG_L, 1, MU, SEQ, 0x4000000, 0x3f000000, { RDST, RSRC, NUM16 } },
286: /* Special case. sac&sachi must occur before rac&rachi because they have
287: intersecting masks! The masks for rac&rachi will match sac&sachi but
288: not the other way around.
289: */
290: { "sac", SHORT_2, 1, IU, PAR|RF0|WF0, 0x5209, 0x7e2f, { RDSTE, ASRC } },
291: { "sachi", SHORT_2, 1, IU, PAR|RF0|WF0, 0x4209, 0x7e0f, { RDST, ASRC } },
292: { "rac", SHORT_2, 1, IU, PAR|WF0, 0x5201, 0x7e21, { RDSTE, ASRC0ONLY, NUM3 } },
293: { "rachi", SHORT_2, 1, IU, PAR|WF0, 0x4201, 0x7e01, { RDST, ASRC, NUM3 } },
294: { "rep", LONG_L, 2, MU, SEQ, 0x27000000, 0x3ff00000, { RSRC, ANUM16 } },
295: { "repi", LONG_L, 2, MU, SEQ, 0x2f000000, 0x3f000000, { UNUM8, ANUM16 } },
296: { "rtd", SHORT_2, 3, MU, ALONE|PAR, 0x5f60, 0x7fff, { 0 } },
297: { "rte", SHORT_2, 3, MU, ALONE|PAR, 0x5f40, 0x7fff, { 0 } },
298: { "sadd", SHORT_2, 1, IU, PAR, 0x1223, 0x7eef, { ADST, ASRC } },
299: { "setf0f", SHORT_2, 1, MU, PAR|RF0, 0x4611, 0x7e1f, { RDST } },
300: { "setf0t", SHORT_2, 1, MU, PAR|RF0, 0x4613, 0x7e1f, { RDST } },
301: { "slae", SHORT_2, 1, IU, PAR, 0x3220, 0x7ee1, { ADST, RSRC } },
302: { "sleep", SHORT_2, 1, MU, ALONE|PAR, 0x5fc0, 0x7fff, { 0 } },
303: { "sll", SHORT_2, 1, IU, PAR, 0x2200, 0x7e01, { RDST, RSRC } },
304: { "sll", SHORT_2, 1, IU, PAR, 0x3200, 0x7ee1, { ADST, RSRC } },
305: { "slli", SHORT_2, 1, IU, PAR, 0x2201, 0x7e01, { RDST, UNUM4 } },
306: { "slli", SHORT_2, 1, IU, PAR, 0x3201, 0x7ee1, { ADST, UNUM4S } },
307: { "slx", SHORT_2, 1, IU, PAR|RF0, 0x460b, 0x7e1f, { RDST } },
308: { "sra", SHORT_2, 1, IU, PAR, 0x2400, 0x7e01, { RDST, RSRC } },
309: { "sra", SHORT_2, 1, IU, PAR, 0x3400, 0x7ee1, { ADST, RSRC } },
310: { "srai", SHORT_2, 1, IU, PAR, 0x2401, 0x7e01, { RDST, UNUM4 } },
311: { "srai", SHORT_2, 1, IU, PAR, 0x3401, 0x7ee1, { ADST, UNUM4S } },
312: { "srl", SHORT_2, 1, IU, PAR, 0x2000, 0x7e01, { RDST, RSRC } },
313: { "srl", SHORT_2, 1, IU, PAR, 0x3000, 0x7ee1, { ADST, RSRC } },
314: { "srli", SHORT_2, 1, IU, PAR, 0x2001, 0x7e01, { RDST, UNUM4 } },
315: { "srli", SHORT_2, 1, IU, PAR, 0x3001, 0x7ee1, { ADST, UNUM4S } },
316: { "srx", SHORT_2, 1, IU, PAR|RF0, 0x4609, 0x7e1f, { RDST } },
317: { "st", LONG_L, 1, MU, SEQ, 0x34000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } },
318: { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6800, 0x7e01, { RSRC2, ATSIGN, RSRC } },
319: { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c1f, 0x7e1f, { RSRC2, ATMINUS, RSRC_SP } },
320: { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6801, 0x7e01, { RSRC2, ATSIGN, RSRC, PLUS } },
321: { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c01, 0x7e01, { RSRC2, ATSIGN, RSRC_NOSP, MINUS } },
322: { "st", LONG_L, 1, MU, SEQ, 0x36010000, 0x3f0f0000, { RSRC2, ATSIGN, NUM16 } },
323: { "st2w", LONG_L, 1, MU, SEQ, 0x35000000, 0x3f100000, { RSRC2E, ATPAR, NUM16, RSRC } },
324: { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a00, 0x7e21, { RSRC2E, ATSIGN, RSRC } },
325: { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e1f, 0x7e3f, { RSRC2E, ATMINUS, RSRC_SP } },
326: { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a01, 0x7e21, { RSRC2E, ATSIGN, RSRC, PLUS } },
327: { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e01, 0x7e21, { RSRC2E, ATSIGN, RSRC_NOSP, MINUS } },
328: { "st2w", LONG_L, 1, MU, SEQ, 0x37010000, 0x3f1f0000, { RSRC2E, ATSIGN, NUM16 } },
329: { "stb", LONG_L, 1, MU, SEQ, 0x3c000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } },
330: { "stb", SHORT_2, 1, MU, PAR|WMEM, 0x7800, 0x7e01, { RSRC2, ATSIGN, RSRC } },
331: { "stop", SHORT_2, 1, MU, ALONE|PAR, 0x5fe0, 0x7fff, { 0 } },
332: { "sub", SHORT_2, 1, EITHER, PAR|WCAR, 0x0, 0x7e01, { RDST, RSRC } },
333: { "sub", SHORT_2, 1, IU, PAR, 0x1001, 0x7ee3, { ADST, RSRC } },
334: { "sub", SHORT_2, 1, IU, PAR, 0x1003, 0x7eef, { ADST, ASRC } },
335: { "sub2w", SHORT_2, 1, IU, PAR|WCAR, 0x1000, 0x7e23, { RDSTE, RSRCE } },
336: { "subac3", LONG_R, 1, IU, SEQ, 0x17000000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } },
337: { "subac3", LONG_R, 1, IU, SEQ, 0x17000002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } },
338: { "subac3s", LONG_R, 1, IU, SEQ, 0x17001000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } },
339: { "subac3s", LONG_R, 1, IU, SEQ, 0x17001002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } },
340: { "subi", SHORT_2, 1, EITHER, PAR, 0x1, 0x7e01, { RDST, UNUM4S } },
341: { "trap", SHORT_2, 5, MU, ALONE|BRANCH_LINK|PAR, 0x5f00, 0x7fe1, { UNUM4 } },
342: { "tst0i", LONG_L, 1, MU, SEQ, 0x7000000, 0x3f0f0000, { RSRC2, NUM16 } },
343: { "tst1i", LONG_L, 1, MU, SEQ, 0xf000000, 0x3f0f0000, { RSRC2, NUM16 } },
344: { "wait", SHORT_2, 1, MU, ALONE|PAR, 0x5f80, 0x7fff, { 0 } },
345: { "xor", SHORT_2, 1, EITHER, PAR, 0xa00, 0x7e01, { RDST, RSRC } },
346: { "xor3", LONG_L, 1, MU, SEQ, 0x5000000, 0x3f000000, { RDST, RSRC, NUM16 } },
347: { 0, 0, 0, 0, 0, 0, 0, { 0 } },
348: };
349:
350:
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