Annotation of src/external/gpl3/binutils.old/dist/include/opcode/riscv-opc.h, Revision 1.5
1.1 christos 1: /* Automatically generated by parse-opcodes */
2: #ifndef RISCV_ENCODING_H
3: #define RISCV_ENCODING_H
4: #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
5: #define MASK_CUSTOM3_RD_RS1_RS2 0x707f
6: #define MATCH_VLSEGSTWU 0xc00305b
7: #define MASK_VLSEGSTWU 0x1e00707f
8: #define MATCH_C_LW0 0x12
9: #define MASK_C_LW0 0x801f
10: #define MATCH_FMV_D_X 0xf2000053
11: #define MASK_FMV_D_X 0xfff0707f
12: #define MATCH_VLH 0x200205b
13: #define MASK_VLH 0xfff0707f
14: #define MATCH_C_LI 0x0
15: #define MASK_C_LI 0x1f
16: #define MATCH_FADD_D 0x2000053
17: #define MASK_FADD_D 0xfe00007f
18: #define MATCH_C_LD 0x9
19: #define MASK_C_LD 0x1f
20: #define MATCH_VLD 0x600205b
21: #define MASK_VLD 0xfff0707f
22: #define MATCH_FADD_S 0x53
23: #define MASK_FADD_S 0xfe00007f
24: #define MATCH_C_LW 0xa
25: #define MASK_C_LW 0x1f
26: #define MATCH_VLW 0x400205b
27: #define MASK_VLW 0xfff0707f
28: #define MATCH_VSSEGSTW 0x400307b
29: #define MASK_VSSEGSTW 0x1e00707f
30: #define MATCH_UTIDX 0x6077
31: #define MASK_UTIDX 0xfffff07f
32: #define MATCH_C_FLW 0x14
33: #define MASK_C_FLW 0x1f
34: #define MATCH_FSUB_D 0xa000053
35: #define MASK_FSUB_D 0xfe00007f
36: #define MATCH_VSSEGSTD 0x600307b
37: #define MASK_VSSEGSTD 0x1e00707f
38: #define MATCH_VSSEGSTB 0x307b
39: #define MASK_VSSEGSTB 0x1e00707f
40: #define MATCH_DIV 0x2004033
41: #define MASK_DIV 0xfe00707f
42: #define MATCH_FMV_H_X 0xf4000053
43: #define MASK_FMV_H_X 0xfff0707f
44: #define MATCH_C_FLD 0x15
45: #define MASK_C_FLD 0x1f
46: #define MATCH_FRRM 0x202073
47: #define MASK_FRRM 0xfffff07f
48: #define MATCH_VFMSV_S 0x1000202b
49: #define MASK_VFMSV_S 0xfff0707f
50: #define MATCH_C_LWSP 0x5
51: #define MASK_C_LWSP 0x1f
52: #define MATCH_FENCE 0xf
53: #define MASK_FENCE 0x707f
54: #define MATCH_FNMSUB_S 0x4b
55: #define MASK_FNMSUB_S 0x600007f
56: #define MATCH_FLE_S 0xa0000053
57: #define MASK_FLE_S 0xfe00707f
58: #define MATCH_FNMSUB_H 0x400004b
59: #define MASK_FNMSUB_H 0x600007f
60: #define MATCH_FLE_H 0xbc000053
61: #define MASK_FLE_H 0xfe00707f
62: #define MATCH_FLW 0x2007
63: #define MASK_FLW 0x707f
64: #define MATCH_VSETVL 0x600b
65: #define MASK_VSETVL 0xfff0707f
66: #define MATCH_VFMSV_D 0x1200202b
67: #define MASK_VFMSV_D 0xfff0707f
68: #define MATCH_FLE_D 0xa2000053
69: #define MASK_FLE_D 0xfe00707f
70: #define MATCH_FENCE_I 0x100f
71: #define MASK_FENCE_I 0x707f
72: #define MATCH_FNMSUB_D 0x200004b
73: #define MASK_FNMSUB_D 0x600007f
74: #define MATCH_ADDW 0x3b
75: #define MASK_ADDW 0xfe00707f
76: #define MATCH_XOR 0x4033
77: #define MASK_XOR 0xfe00707f
78: #define MATCH_SUB 0x40000033
79: #define MASK_SUB 0xfe00707f
80: #define MATCH_VSSTW 0x400307b
81: #define MASK_VSSTW 0xfe00707f
82: #define MATCH_VSSTH 0x200307b
83: #define MASK_VSSTH 0xfe00707f
84: #define MATCH_SC_W 0x1800202f
85: #define MASK_SC_W 0xf800707f
86: #define MATCH_VSSTB 0x307b
87: #define MASK_VSSTB 0xfe00707f
88: #define MATCH_VSSTD 0x600307b
89: #define MASK_VSSTD 0xfe00707f
90: #define MATCH_ADDI 0x13
91: #define MASK_ADDI 0x707f
92: #define MATCH_RDTIMEH 0xc8102073
93: #define MASK_RDTIMEH 0xfffff07f
94: #define MATCH_MULH 0x2001033
95: #define MASK_MULH 0xfe00707f
96: #define MATCH_CSRRSI 0x6073
97: #define MASK_CSRRSI 0x707f
98: #define MATCH_FCVT_D_WU 0xd2100053
99: #define MASK_FCVT_D_WU 0xfff0007f
100: #define MATCH_MULW 0x200003b
101: #define MASK_MULW 0xfe00707f
102: #define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
103: #define MASK_CUSTOM1_RD_RS1_RS2 0x707f
104: #define MATCH_VENQIMM1 0xc00302b
105: #define MASK_VENQIMM1 0xfe007fff
106: #define MATCH_VENQIMM2 0xe00302b
107: #define MASK_VENQIMM2 0xfe007fff
108: #define MATCH_RDINSTRET 0xc0202073
109: #define MASK_RDINSTRET 0xfffff07f
110: #define MATCH_C_SWSP 0x8
111: #define MASK_C_SWSP 0x1f
112: #define MATCH_VLSTW 0x400305b
113: #define MASK_VLSTW 0xfe00707f
114: #define MATCH_VLSTH 0x200305b
115: #define MASK_VLSTH 0xfe00707f
116: #define MATCH_VLSTB 0x305b
117: #define MASK_VLSTB 0xfe00707f
118: #define MATCH_VLSTD 0x600305b
119: #define MASK_VLSTD 0xfe00707f
120: #define MATCH_ANDI 0x7013
121: #define MASK_ANDI 0x707f
122: #define MATCH_FMV_X_S 0xe0000053
123: #define MASK_FMV_X_S 0xfff0707f
124: #define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
125: #define MASK_CUSTOM0_RD_RS1_RS2 0x707f
126: #define MATCH_FNMADD_S 0x4f
127: #define MASK_FNMADD_S 0x600007f
128: #define MATCH_LWU 0x6003
129: #define MASK_LWU 0x707f
130: #define MATCH_CUSTOM0_RS1 0x200b
131: #define MASK_CUSTOM0_RS1 0x707f
132: #define MATCH_VLSEGSTBU 0x800305b
133: #define MASK_VLSEGSTBU 0x1e00707f
134: #define MATCH_FNMADD_D 0x200004f
135: #define MASK_FNMADD_D 0x600007f
136: #define MATCH_FCVT_W_S 0xc0000053
137: #define MASK_FCVT_W_S 0xfff0007f
138: #define MATCH_C_SRAI 0x1019
139: #define MASK_C_SRAI 0x1c1f
140: #define MATCH_MULHSU 0x2002033
141: #define MASK_MULHSU 0xfe00707f
142: #define MATCH_FCVT_D_LU 0xd2300053
143: #define MASK_FCVT_D_LU 0xfff0007f
144: #define MATCH_FCVT_W_D 0xc2000053
145: #define MASK_FCVT_W_D 0xfff0007f
146: #define MATCH_FSUB_H 0xc000053
147: #define MASK_FSUB_H 0xfe00007f
148: #define MATCH_DIVUW 0x200503b
149: #define MASK_DIVUW 0xfe00707f
150: #define MATCH_SLTI 0x2013
151: #define MASK_SLTI 0x707f
152: #define MATCH_VLSTBU 0x800305b
153: #define MASK_VLSTBU 0xfe00707f
154: #define MATCH_SLTU 0x3033
155: #define MASK_SLTU 0xfe00707f
156: #define MATCH_FLH 0x1007
157: #define MASK_FLH 0x707f
158: #define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
159: #define MASK_CUSTOM2_RD_RS1_RS2 0x707f
160: #define MATCH_FLD 0x3007
161: #define MASK_FLD 0x707f
162: #define MATCH_FSUB_S 0x8000053
163: #define MASK_FSUB_S 0xfe00007f
164: #define MATCH_FCVT_H_LU 0x6c000053
165: #define MASK_FCVT_H_LU 0xfff0007f
166: #define MATCH_CUSTOM0 0xb
167: #define MASK_CUSTOM0 0x707f
168: #define MATCH_CUSTOM1 0x2b
169: #define MASK_CUSTOM1 0x707f
170: #define MATCH_CUSTOM2 0x5b
171: #define MASK_CUSTOM2 0x707f
172: #define MATCH_CUSTOM3 0x7b
173: #define MASK_CUSTOM3 0x707f
174: #define MATCH_VXCPTSAVE 0x302b
175: #define MASK_VXCPTSAVE 0xfff07fff
176: #define MATCH_VMSV 0x200202b
177: #define MASK_VMSV 0xfff0707f
178: #define MATCH_FCVT_LU_S 0xc0300053
179: #define MASK_FCVT_LU_S 0xfff0007f
180: #define MATCH_AUIPC 0x17
181: #define MASK_AUIPC 0x7f
182: #define MATCH_FRFLAGS 0x102073
183: #define MASK_FRFLAGS 0xfffff07f
184: #define MATCH_FCVT_LU_D 0xc2300053
185: #define MASK_FCVT_LU_D 0xfff0007f
186: #define MATCH_CSRRWI 0x5073
187: #define MASK_CSRRWI 0x707f
188: #define MATCH_FADD_H 0x4000053
189: #define MASK_FADD_H 0xfe00007f
190: #define MATCH_FSQRT_S 0x58000053
191: #define MASK_FSQRT_S 0xfff0007f
192: #define MATCH_VXCPTKILL 0x400302b
193: #define MASK_VXCPTKILL 0xffffffff
194: #define MATCH_STOP 0x5077
195: #define MASK_STOP 0xffffffff
196: #define MATCH_FSGNJN_S 0x20001053
197: #define MASK_FSGNJN_S 0xfe00707f
198: #define MATCH_FSGNJN_H 0x34000053
199: #define MASK_FSGNJN_H 0xfe00707f
200: #define MATCH_FSQRT_D 0x5a000053
201: #define MASK_FSQRT_D 0xfff0007f
202: #define MATCH_XORI 0x4013
203: #define MASK_XORI 0x707f
204: #define MATCH_DIVU 0x2005033
205: #define MASK_DIVU 0xfe00707f
206: #define MATCH_FSGNJN_D 0x22001053
207: #define MASK_FSGNJN_D 0xfe00707f
208: #define MATCH_FSQRT_H 0x24000053
209: #define MASK_FSQRT_H 0xfff0007f
210: #define MATCH_VSSEGSTH 0x200307b
211: #define MASK_VSSEGSTH 0x1e00707f
212: #define MATCH_SW 0x2023
213: #define MASK_SW 0x707f
214: #define MATCH_VLSTWU 0xc00305b
215: #define MASK_VLSTWU 0xfe00707f
216: #define MATCH_VFSSEGW 0x1400207b
217: #define MASK_VFSSEGW 0x1ff0707f
218: #define MATCH_LHU 0x5003
219: #define MASK_LHU 0x707f
220: #define MATCH_SH 0x1023
221: #define MASK_SH 0x707f
222: #define MATCH_FMSUB_H 0x4000047
223: #define MASK_FMSUB_H 0x600007f
224: #define MATCH_VXCPTAUX 0x200402b
225: #define MASK_VXCPTAUX 0xfffff07f
226: #define MATCH_FMSUB_D 0x2000047
227: #define MASK_FMSUB_D 0x600007f
228: #define MATCH_VFSSEGD 0x1600207b
229: #define MASK_VFSSEGD 0x1ff0707f
230: #define MATCH_VLSEGHU 0xa00205b
231: #define MASK_VLSEGHU 0x1ff0707f
232: #define MATCH_MOVN 0x2007077
233: #define MASK_MOVN 0xfe00707f
234: #define MATCH_CUSTOM1_RS1 0x202b
235: #define MASK_CUSTOM1_RS1 0x707f
236: #define MATCH_VLSTHU 0xa00305b
237: #define MASK_VLSTHU 0xfe00707f
238: #define MATCH_MOVZ 0x7077
239: #define MASK_MOVZ 0xfe00707f
240: #define MATCH_CSRRW 0x1073
241: #define MASK_CSRRW 0x707f
242: #define MATCH_LD 0x3003
243: #define MASK_LD 0x707f
244: #define MATCH_LB 0x3
245: #define MASK_LB 0x707f
246: #define MATCH_VLWU 0xc00205b
247: #define MASK_VLWU 0xfff0707f
248: #define MATCH_LH 0x1003
249: #define MASK_LH 0x707f
250: #define MATCH_LW 0x2003
251: #define MASK_LW 0x707f
252: #define MATCH_CSRRC 0x3073
253: #define MASK_CSRRC 0x707f
254: #define MATCH_FCVT_LU_H 0x4c000053
255: #define MASK_FCVT_LU_H 0xfff0007f
256: #define MATCH_FCVT_S_D 0x40100053
257: #define MASK_FCVT_S_D 0xfff0007f
258: #define MATCH_BGEU 0x7063
259: #define MASK_BGEU 0x707f
260: #define MATCH_VFLSTD 0x1600305b
261: #define MASK_VFLSTD 0xfe00707f
262: #define MATCH_FCVT_S_L 0xd0200053
263: #define MASK_FCVT_S_L 0xfff0007f
264: #define MATCH_FCVT_S_H 0x84000053
265: #define MASK_FCVT_S_H 0xfff0007f
266: #define MATCH_FSCSR 0x301073
267: #define MASK_FSCSR 0xfff0707f
268: #define MATCH_FCVT_S_W 0xd0000053
269: #define MASK_FCVT_S_W 0xfff0007f
270: #define MATCH_VFLSTW 0x1400305b
271: #define MASK_VFLSTW 0xfe00707f
272: #define MATCH_VXCPTEVAC 0x600302b
273: #define MASK_VXCPTEVAC 0xfff07fff
274: #define MATCH_AMOMINU_D 0xc000302f
275: #define MASK_AMOMINU_D 0xf800707f
276: #define MATCH_FSFLAGS 0x101073
277: #define MASK_FSFLAGS 0xfff0707f
278: #define MATCH_SRLI 0x5013
279: #define MASK_SRLI 0xfc00707f
280: #define MATCH_C_SRLI 0x819
281: #define MASK_C_SRLI 0x1c1f
282: #define MATCH_AMOMINU_W 0xc000202f
283: #define MASK_AMOMINU_W 0xf800707f
284: #define MATCH_SRLW 0x503b
285: #define MASK_SRLW 0xfe00707f
286: #define MATCH_VFLSEGW 0x1400205b
287: #define MASK_VFLSEGW 0x1ff0707f
288: #define MATCH_C_LD0 0x8012
289: #define MASK_C_LD0 0x801f
290: #define MATCH_VLSEGBU 0x800205b
291: #define MASK_VLSEGBU 0x1ff0707f
292: #define MATCH_JALR 0x67
293: #define MASK_JALR 0x707f
294: #define MATCH_BLT 0x4063
295: #define MASK_BLT 0x707f
296: #define MATCH_CUSTOM2_RD_RS1 0x605b
297: #define MASK_CUSTOM2_RD_RS1 0x707f
298: #define MATCH_FCLASS_S 0xe0001053
299: #define MASK_FCLASS_S 0xfff0707f
300: #define MATCH_SFENCE_VM 0x10100073
301: #define MASK_SFENCE_VM 0xfff07fff
302: #define MATCH_REM 0x2006033
303: #define MASK_REM 0xfe00707f
304: #define MATCH_FCLASS_D 0xe2001053
305: #define MASK_FCLASS_D 0xfff0707f
306: #define MATCH_FMUL_S 0x10000053
307: #define MASK_FMUL_S 0xfe00007f
308: #define MATCH_RDCYCLEH 0xc8002073
309: #define MASK_RDCYCLEH 0xfffff07f
310: #define MATCH_VLSEGSTHU 0xa00305b
311: #define MASK_VLSEGSTHU 0x1e00707f
312: #define MATCH_FMUL_D 0x12000053
313: #define MASK_FMUL_D 0xfe00007f
314: #define MATCH_ORI 0x6013
315: #define MASK_ORI 0x707f
316: #define MATCH_FMUL_H 0x14000053
317: #define MASK_FMUL_H 0xfe00007f
318: #define MATCH_VFLSEGD 0x1600205b
319: #define MASK_VFLSEGD 0x1ff0707f
320: #define MATCH_FEQ_S 0xa0002053
321: #define MASK_FEQ_S 0xfe00707f
322: #define MATCH_FSGNJX_D 0x22002053
323: #define MASK_FSGNJX_D 0xfe00707f
324: #define MATCH_SRAIW 0x4000501b
325: #define MASK_SRAIW 0xfe00707f
326: #define MATCH_FSGNJX_H 0x3c000053
327: #define MASK_FSGNJX_H 0xfe00707f
328: #define MATCH_FSGNJX_S 0x20002053
329: #define MASK_FSGNJX_S 0xfe00707f
330: #define MATCH_FEQ_D 0xa2002053
331: #define MASK_FEQ_D 0xfe00707f
332: #define MATCH_CUSTOM1_RD_RS1 0x602b
333: #define MASK_CUSTOM1_RD_RS1 0x707f
334: #define MATCH_FEQ_H 0xac000053
335: #define MASK_FEQ_H 0xfe00707f
336: #define MATCH_AMOMAXU_D 0xe000302f
337: #define MASK_AMOMAXU_D 0xf800707f
338: #define MATCH_DIVW 0x200403b
339: #define MASK_DIVW 0xfe00707f
340: #define MATCH_AMOMAXU_W 0xe000202f
341: #define MASK_AMOMAXU_W 0xf800707f
342: #define MATCH_SRAI_RV32 0x40005013
343: #define MASK_SRAI_RV32 0xfe00707f
344: #define MATCH_C_SRLI32 0xc19
345: #define MASK_C_SRLI32 0x1c1f
346: #define MATCH_VFSSTW 0x1400307b
347: #define MASK_VFSSTW 0xfe00707f
348: #define MATCH_CUSTOM0_RD 0x400b
349: #define MASK_CUSTOM0_RD 0x707f
350: #define MATCH_C_BEQ 0x10
351: #define MASK_C_BEQ 0x1f
352: #define MATCH_VFSSTD 0x1600307b
353: #define MASK_VFSSTD 0xfe00707f
354: #define MATCH_CUSTOM3_RD_RS1 0x607b
355: #define MASK_CUSTOM3_RD_RS1 0x707f
356: #define MATCH_LR_D 0x1000302f
357: #define MASK_LR_D 0xf9f0707f
358: #define MATCH_LR_W 0x1000202f
359: #define MASK_LR_W 0xf9f0707f
360: #define MATCH_FCVT_H_WU 0x7c000053
361: #define MASK_FCVT_H_WU 0xfff0007f
362: #define MATCH_VMVV 0x200002b
363: #define MASK_VMVV 0xfff0707f
364: #define MATCH_SLLW 0x103b
365: #define MASK_SLLW 0xfe00707f
366: #define MATCH_SLLI 0x1013
367: #define MASK_SLLI 0xfc00707f
368: #define MATCH_BEQ 0x63
369: #define MASK_BEQ 0x707f
370: #define MATCH_AND 0x7033
371: #define MASK_AND 0xfe00707f
372: #define MATCH_LBU 0x4003
373: #define MASK_LBU 0x707f
374: #define MATCH_FSGNJ_S 0x20000053
375: #define MASK_FSGNJ_S 0xfe00707f
376: #define MATCH_FMSUB_S 0x47
377: #define MASK_FMSUB_S 0x600007f
378: #define MATCH_C_SUB3 0x11c
379: #define MASK_C_SUB3 0x31f
380: #define MATCH_FSGNJ_H 0x2c000053
381: #define MASK_FSGNJ_H 0xfe00707f
382: #define MATCH_VLB 0x205b
383: #define MASK_VLB 0xfff0707f
384: #define MATCH_C_ADDIW 0x1d
385: #define MASK_C_ADDIW 0x1f
386: #define MATCH_CUSTOM3_RS1_RS2 0x307b
387: #define MASK_CUSTOM3_RS1_RS2 0x707f
388: #define MATCH_FSGNJ_D 0x22000053
389: #define MASK_FSGNJ_D 0xfe00707f
390: #define MATCH_VLSEGWU 0xc00205b
391: #define MASK_VLSEGWU 0x1ff0707f
392: #define MATCH_FCVT_S_WU 0xd0100053
393: #define MASK_FCVT_S_WU 0xfff0007f
394: #define MATCH_CUSTOM3_RS1 0x207b
395: #define MASK_CUSTOM3_RS1 0x707f
396: #define MATCH_SC_D 0x1800302f
397: #define MASK_SC_D 0xf800707f
398: #define MATCH_VFSW 0x1400207b
399: #define MASK_VFSW 0xfff0707f
400: #define MATCH_AMOSWAP_D 0x800302f
401: #define MASK_AMOSWAP_D 0xf800707f
402: #define MATCH_SB 0x23
403: #define MASK_SB 0x707f
404: #define MATCH_AMOSWAP_W 0x800202f
405: #define MASK_AMOSWAP_W 0xf800707f
406: #define MATCH_VFSD 0x1600207b
407: #define MASK_VFSD 0xfff0707f
408: #define MATCH_CUSTOM2_RS1 0x205b
409: #define MASK_CUSTOM2_RS1 0x707f
410: #define MATCH_SD 0x3023
411: #define MASK_SD 0x707f
412: #define MATCH_FMV_S_X 0xf0000053
413: #define MASK_FMV_S_X 0xfff0707f
414: #define MATCH_REMUW 0x200703b
415: #define MASK_REMUW 0xfe00707f
416: #define MATCH_JAL 0x6f
417: #define MASK_JAL 0x7f
418: #define MATCH_C_FSD 0x18
419: #define MASK_C_FSD 0x1f
420: #define MATCH_RDCYCLE 0xc0002073
421: #define MASK_RDCYCLE 0xfffff07f
422: #define MATCH_C_BNE 0x11
423: #define MASK_C_BNE 0x1f
424: #define MATCH_C_ADD 0x1a
425: #define MASK_C_ADD 0x801f
426: #define MATCH_VXCPTCAUSE 0x402b
427: #define MASK_VXCPTCAUSE 0xfffff07f
428: #define MATCH_VGETCFG 0x400b
429: #define MASK_VGETCFG 0xfffff07f
430: #define MATCH_LUI 0x37
431: #define MASK_LUI 0x7f
432: #define MATCH_VSETCFG 0x200b
433: #define MASK_VSETCFG 0x7fff
434: #define MATCH_C_SDSP 0x6
435: #define MASK_C_SDSP 0x1f
436: #define MATCH_C_LDSP 0x4
437: #define MASK_C_LDSP 0x1f
438: #define MATCH_FNMADD_H 0x400004f
439: #define MASK_FNMADD_H 0x600007f
440: #define MATCH_CUSTOM0_RS1_RS2 0x300b
441: #define MASK_CUSTOM0_RS1_RS2 0x707f
442: #define MATCH_SLLI_RV32 0x1013
443: #define MASK_SLLI_RV32 0xfe00707f
444: #define MATCH_MUL 0x2000033
445: #define MASK_MUL 0xfe00707f
446: #define MATCH_CSRRCI 0x7073
447: #define MASK_CSRRCI 0x707f
448: #define MATCH_C_SRAI32 0x1419
449: #define MASK_C_SRAI32 0x1c1f
450: #define MATCH_FLT_H 0xb4000053
451: #define MASK_FLT_H 0xfe00707f
452: #define MATCH_SRAI 0x40005013
453: #define MASK_SRAI 0xfc00707f
454: #define MATCH_AMOAND_D 0x6000302f
455: #define MASK_AMOAND_D 0xf800707f
456: #define MATCH_FLT_D 0xa2001053
457: #define MASK_FLT_D 0xfe00707f
458: #define MATCH_SRAW 0x4000503b
459: #define MASK_SRAW 0xfe00707f
460: #define MATCH_CSRRS 0x2073
461: #define MASK_CSRRS 0x707f
462: #define MATCH_FLT_S 0xa0001053
463: #define MASK_FLT_S 0xfe00707f
464: #define MATCH_ADDIW 0x1b
465: #define MASK_ADDIW 0x707f
466: #define MATCH_AMOAND_W 0x6000202f
467: #define MASK_AMOAND_W 0xf800707f
468: #define MATCH_CUSTOM2_RD 0x405b
469: #define MASK_CUSTOM2_RD 0x707f
470: #define MATCH_MRTS 0x30500073
471: #define MASK_MRTS 0xffffffff
472: #define MATCH_FCVT_WU_D 0xc2100053
473: #define MASK_FCVT_WU_D 0xfff0007f
474: #define MATCH_AMOXOR_W 0x2000202f
475: #define MASK_AMOXOR_W 0xf800707f
476: #define MATCH_FCVT_D_L 0xd2200053
477: #define MASK_FCVT_D_L 0xfff0007f
478: #define MATCH_FCVT_WU_H 0x5c000053
479: #define MASK_FCVT_WU_H 0xfff0007f
480: #define MATCH_C_SLLI 0x19
481: #define MASK_C_SLLI 0x1c1f
482: #define MATCH_AMOXOR_D 0x2000302f
483: #define MASK_AMOXOR_D 0xf800707f
484: #define MATCH_FCVT_WU_S 0xc0100053
485: #define MASK_FCVT_WU_S 0xfff0007f
486: #define MATCH_CUSTOM3_RD 0x407b
487: #define MASK_CUSTOM3_RD 0x707f
488: #define MATCH_FMAX_H 0xcc000053
489: #define MASK_FMAX_H 0xfe00707f
490: #define MATCH_VENQCNT 0x1000302b
491: #define MASK_VENQCNT 0xfe007fff
492: #define MATCH_VLBU 0x800205b
493: #define MASK_VLBU 0xfff0707f
494: #define MATCH_VLHU 0xa00205b
495: #define MASK_VLHU 0xfff0707f
496: #define MATCH_C_SW 0xd
497: #define MASK_C_SW 0x1f
498: #define MATCH_C_SD 0xc
499: #define MASK_C_SD 0x1f
500: #define MATCH_C_OR3 0x21c
501: #define MASK_C_OR3 0x31f
502: #define MATCH_C_AND3 0x31c
503: #define MASK_C_AND3 0x31f
504: #define MATCH_VFSSEGSTW 0x1400307b
505: #define MASK_VFSSEGSTW 0x1e00707f
506: #define MATCH_SLT 0x2033
507: #define MASK_SLT 0xfe00707f
508: #define MATCH_AMOOR_D 0x4000302f
509: #define MASK_AMOOR_D 0xf800707f
510: #define MATCH_REMU 0x2007033
511: #define MASK_REMU 0xfe00707f
512: #define MATCH_REMW 0x200603b
513: #define MASK_REMW 0xfe00707f
514: #define MATCH_SLL 0x1033
515: #define MASK_SLL 0xfe00707f
516: #define MATCH_VFSSEGSTD 0x1600307b
517: #define MASK_VFSSEGSTD 0x1e00707f
518: #define MATCH_AMOOR_W 0x4000202f
519: #define MASK_AMOOR_W 0xf800707f
520: #define MATCH_CUSTOM2_RS1_RS2 0x305b
521: #define MASK_CUSTOM2_RS1_RS2 0x707f
522: #define MATCH_VF 0x10202b
523: #define MASK_VF 0x1f0707f
524: #define MATCH_VFMVV 0x1000002b
525: #define MASK_VFMVV 0xfff0707f
526: #define MATCH_VFLSEGSTW 0x1400305b
527: #define MASK_VFLSEGSTW 0x1e00707f
528: #define MATCH_VXCPTRESTORE 0x200302b
529: #define MASK_VXCPTRESTORE 0xfff07fff
530: #define MATCH_VXCPTHOLD 0x800302b
531: #define MASK_VXCPTHOLD 0xfff07fff
532: #define MATCH_SLTIU 0x3013
533: #define MASK_SLTIU 0x707f
534: #define MATCH_VFLSEGSTD 0x1600305b
535: #define MASK_VFLSEGSTD 0x1e00707f
536: #define MATCH_VFLD 0x1600205b
537: #define MASK_VFLD 0xfff0707f
538: #define MATCH_FMADD_S 0x43
539: #define MASK_FMADD_S 0x600007f
540: #define MATCH_VFLW 0x1400205b
541: #define MASK_VFLW 0xfff0707f
542: #define MATCH_FMADD_D 0x2000043
543: #define MASK_FMADD_D 0x600007f
544: #define MATCH_FMADD_H 0x4000043
545: #define MASK_FMADD_H 0x600007f
546: #define MATCH_SRET 0x10000073
547: #define MASK_SRET 0xffffffff
548: #define MATCH_VSSEGW 0x400207b
549: #define MASK_VSSEGW 0x1ff0707f
550: #define MATCH_CUSTOM0_RD_RS1 0x600b
551: #define MASK_CUSTOM0_RD_RS1 0x707f
552: #define MATCH_VSSEGH 0x200207b
553: #define MASK_VSSEGH 0x1ff0707f
554: #define MATCH_FRCSR 0x302073
555: #define MASK_FRCSR 0xfffff07f
556: #define MATCH_VSSEGD 0x600207b
557: #define MASK_VSSEGD 0x1ff0707f
558: #define MATCH_VSSEGB 0x207b
559: #define MASK_VSSEGB 0x1ff0707f
560: #define MATCH_FMIN_H 0xc4000053
561: #define MASK_FMIN_H 0xfe00707f
562: #define MATCH_FMIN_D 0x2a000053
563: #define MASK_FMIN_D 0xfe00707f
564: #define MATCH_BLTU 0x6063
565: #define MASK_BLTU 0x707f
566: #define MATCH_FMIN_S 0x28000053
567: #define MASK_FMIN_S 0xfe00707f
568: #define MATCH_SRLI_RV32 0x5013
569: #define MASK_SRLI_RV32 0xfe00707f
570: #define MATCH_SLLIW 0x101b
571: #define MASK_SLLIW 0xfe00707f
572: #define MATCH_FMAX_S 0x28001053
573: #define MASK_FMAX_S 0xfe00707f
574: #define MATCH_FCVT_D_H 0x8c000053
575: #define MASK_FCVT_D_H 0xfff0007f
576: #define MATCH_FCVT_D_W 0xd2000053
577: #define MASK_FCVT_D_W 0xfff0007f
578: #define MATCH_ADD 0x33
579: #define MASK_ADD 0xfe00707f
580: #define MATCH_FCVT_D_S 0x42000053
581: #define MASK_FCVT_D_S 0xfff0007f
582: #define MATCH_FMAX_D 0x2a001053
583: #define MASK_FMAX_D 0xfe00707f
584: #define MATCH_BNE 0x1063
585: #define MASK_BNE 0x707f
586: #define MATCH_CUSTOM1_RD 0x402b
587: #define MASK_CUSTOM1_RD 0x707f
588: #define MATCH_FSRM 0x201073
589: #define MASK_FSRM 0xfff0707f
590: #define MATCH_FDIV_D 0x1a000053
591: #define MASK_FDIV_D 0xfe00007f
592: #define MATCH_VSW 0x400207b
593: #define MASK_VSW 0xfff0707f
594: #define MATCH_FCVT_L_S 0xc0200053
595: #define MASK_FCVT_L_S 0xfff0007f
596: #define MATCH_FDIV_H 0x1c000053
597: #define MASK_FDIV_H 0xfe00007f
598: #define MATCH_VSB 0x207b
599: #define MASK_VSB 0xfff0707f
600: #define MATCH_FDIV_S 0x18000053
601: #define MASK_FDIV_S 0xfe00007f
602: #define MATCH_FSRMI 0x205073
603: #define MASK_FSRMI 0xfff0707f
604: #define MATCH_FCVT_L_H 0x44000053
605: #define MASK_FCVT_L_H 0xfff0007f
606: #define MATCH_VSH 0x200207b
607: #define MASK_VSH 0xfff0707f
608: #define MATCH_FCVT_L_D 0xc2200053
609: #define MASK_FCVT_L_D 0xfff0007f
610: #define MATCH_FCVT_H_S 0x90000053
611: #define MASK_FCVT_H_S 0xfff0007f
612: #define MATCH_SCALL 0x73
613: #define MASK_SCALL 0xffffffff
614: #define MATCH_FSFLAGSI 0x105073
615: #define MASK_FSFLAGSI 0xfff0707f
616: #define MATCH_FCVT_H_W 0x74000053
617: #define MASK_FCVT_H_W 0xfff0007f
618: #define MATCH_FCVT_H_L 0x64000053
619: #define MASK_FCVT_H_L 0xfff0007f
620: #define MATCH_SRLIW 0x501b
621: #define MASK_SRLIW 0xfe00707f
622: #define MATCH_FCVT_S_LU 0xd0300053
623: #define MASK_FCVT_S_LU 0xfff0007f
624: #define MATCH_FCVT_H_D 0x92000053
625: #define MASK_FCVT_H_D 0xfff0007f
626: #define MATCH_SBREAK 0x100073
627: #define MASK_SBREAK 0xffffffff
628: #define MATCH_RDINSTRETH 0xc8202073
629: #define MASK_RDINSTRETH 0xfffff07f
630: #define MATCH_SRA 0x40005033
631: #define MASK_SRA 0xfe00707f
632: #define MATCH_BGE 0x5063
633: #define MASK_BGE 0x707f
634: #define MATCH_SRL 0x5033
635: #define MASK_SRL 0xfe00707f
636: #define MATCH_VENQCMD 0xa00302b
637: #define MASK_VENQCMD 0xfe007fff
638: #define MATCH_OR 0x6033
639: #define MASK_OR 0xfe00707f
640: #define MATCH_SUBW 0x4000003b
641: #define MASK_SUBW 0xfe00707f
642: #define MATCH_FMV_X_D 0xe2000053
643: #define MASK_FMV_X_D 0xfff0707f
644: #define MATCH_RDTIME 0xc0102073
645: #define MASK_RDTIME 0xfffff07f
646: #define MATCH_AMOADD_D 0x302f
647: #define MASK_AMOADD_D 0xf800707f
648: #define MATCH_AMOMAX_W 0xa000202f
649: #define MASK_AMOMAX_W 0xf800707f
650: #define MATCH_C_MOVE 0x2
651: #define MASK_C_MOVE 0x801f
652: #define MATCH_FMOVN 0x6007077
653: #define MASK_FMOVN 0xfe00707f
654: #define MATCH_C_FSW 0x16
655: #define MASK_C_FSW 0x1f
656: #define MATCH_AMOADD_W 0x202f
657: #define MASK_AMOADD_W 0xf800707f
658: #define MATCH_AMOMAX_D 0xa000302f
659: #define MASK_AMOMAX_D 0xf800707f
660: #define MATCH_FMOVZ 0x4007077
661: #define MASK_FMOVZ 0xfe00707f
662: #define MATCH_CUSTOM1_RS1_RS2 0x302b
663: #define MASK_CUSTOM1_RS1_RS2 0x707f
664: #define MATCH_FMV_X_H 0xe4000053
665: #define MASK_FMV_X_H 0xfff0707f
666: #define MATCH_VSD 0x600207b
667: #define MASK_VSD 0xfff0707f
668: #define MATCH_VLSEGSTW 0x400305b
669: #define MASK_VLSEGSTW 0x1e00707f
670: #define MATCH_C_ADDI 0x1
671: #define MASK_C_ADDI 0x1f
672: #define MATCH_C_SLLIW 0x1819
673: #define MASK_C_SLLIW 0x1c1f
674: #define MATCH_VLSEGSTB 0x305b
675: #define MASK_VLSEGSTB 0x1e00707f
676: #define MATCH_VLSEGSTD 0x600305b
677: #define MASK_VLSEGSTD 0x1e00707f
678: #define MATCH_VLSEGSTH 0x200305b
679: #define MASK_VLSEGSTH 0x1e00707f
680: #define MATCH_MULHU 0x2003033
681: #define MASK_MULHU 0xfe00707f
682: #define MATCH_AMOMIN_W 0x8000202f
683: #define MASK_AMOMIN_W 0xf800707f
684: #define MATCH_C_SLLI32 0x419
685: #define MASK_C_SLLI32 0x1c1f
686: #define MATCH_C_ADD3 0x1c
687: #define MASK_C_ADD3 0x31f
688: #define MATCH_VGETVL 0x200400b
689: #define MASK_VGETVL 0xfffff07f
690: #define MATCH_AMOMIN_D 0x8000302f
691: #define MASK_AMOMIN_D 0xf800707f
692: #define MATCH_FCVT_W_H 0x54000053
693: #define MASK_FCVT_W_H 0xfff0007f
694: #define MATCH_VLSEGB 0x205b
695: #define MASK_VLSEGB 0x1ff0707f
696: #define MATCH_FSD 0x3027
697: #define MASK_FSD 0x707f
698: #define MATCH_VLSEGD 0x600205b
699: #define MASK_VLSEGD 0x1ff0707f
700: #define MATCH_FSH 0x1027
701: #define MASK_FSH 0x707f
702: #define MATCH_VLSEGH 0x200205b
703: #define MASK_VLSEGH 0x1ff0707f
704: #define MATCH_C_SUB 0x801a
705: #define MASK_C_SUB 0x801f
706: #define MATCH_VLSEGW 0x400205b
707: #define MASK_VLSEGW 0x1ff0707f
708: #define MATCH_FSW 0x2027
709: #define MASK_FSW 0x707f
710: #define MATCH_C_J 0x8002
711: #define MASK_C_J 0x801f
712: #define CSR_FFLAGS 0x1
713: #define CSR_FRM 0x2
714: #define CSR_FCSR 0x3
715: #define CSR_CYCLE 0xc00
716: #define CSR_TIME 0xc01
717: #define CSR_INSTRET 0xc02
718: #define CSR_STATS 0xc0
719: #define CSR_UARCH0 0xcc0
720: #define CSR_UARCH1 0xcc1
721: #define CSR_UARCH2 0xcc2
722: #define CSR_UARCH3 0xcc3
723: #define CSR_UARCH4 0xcc4
724: #define CSR_UARCH5 0xcc5
725: #define CSR_UARCH6 0xcc6
726: #define CSR_UARCH7 0xcc7
727: #define CSR_UARCH8 0xcc8
728: #define CSR_UARCH9 0xcc9
729: #define CSR_UARCH10 0xcca
730: #define CSR_UARCH11 0xccb
731: #define CSR_UARCH12 0xccc
732: #define CSR_UARCH13 0xccd
733: #define CSR_UARCH14 0xcce
734: #define CSR_UARCH15 0xccf
735: #define CSR_SSTATUS 0x100
736: #define CSR_STVEC 0x101
737: #define CSR_STIMECMP 0x121
738: #define CSR_SSCRATCH 0x140
739: #define CSR_SEPC 0x141
740: #define CSR_SPTBR 0x188
741: #define CSR_SASID 0x189
742: #define CSR_SCYCLE 0x900
743: #define CSR_STIME 0x901
744: #define CSR_SINSTRET 0x902
745: #define CSR_SCAUSE 0xd40
746: #define CSR_SBADADDR 0xd41
747: #define CSR_MSTATUS 0x300
748: #define CSR_MSCRATCH 0x340
749: #define CSR_MEPC 0x341
750: #define CSR_MCAUSE 0x342
751: #define CSR_MBADADDR 0x343
752: #define CSR_RESET 0x780
753: #define CSR_TOHOST 0x781
754: #define CSR_FROMHOST 0x782
755: #define CSR_SEND_IPI 0x783
756: #define CSR_HARTID 0xfc0
757: #define CSR_CYCLEH 0xc80
758: #define CSR_TIMEH 0xc81
759: #define CSR_INSTRETH 0xc82
760: #define CSR_SCYCLEH 0x980
761: #define CSR_STIMEH 0x981
762: #define CSR_SINSTRETH 0x982
763: #define CAUSE_MISALIGNED_FETCH 0x0
764: #define CAUSE_FAULT_FETCH 0x1
765: #define CAUSE_ILLEGAL_INSTRUCTION 0x2
766: #define CAUSE_MISALIGNED_LOAD 0x4
767: #define CAUSE_FAULT_LOAD 0x5
768: #define CAUSE_MISALIGNED_STORE 0x6
769: #define CAUSE_FAULT_STORE 0x7
770: #define CAUSE_ECALL 0x8
771: #define CAUSE_BREAKPOINT 0x9
772: #endif
773: #ifdef DECLARE_INSN
774: DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
775: DECLARE_INSN(vlsegstwu, MATCH_VLSEGSTWU, MASK_VLSEGSTWU)
776: DECLARE_INSN(c_lw0, MATCH_C_LW0, MASK_C_LW0)
777: DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
778: DECLARE_INSN(vlh, MATCH_VLH, MASK_VLH)
779: DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
780: DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
781: DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
782: DECLARE_INSN(vld, MATCH_VLD, MASK_VLD)
783: DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
784: DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
785: DECLARE_INSN(vlw, MATCH_VLW, MASK_VLW)
786: DECLARE_INSN(vssegstw, MATCH_VSSEGSTW, MASK_VSSEGSTW)
787: DECLARE_INSN(utidx, MATCH_UTIDX, MASK_UTIDX)
788: DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
789: DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
790: DECLARE_INSN(vssegstd, MATCH_VSSEGSTD, MASK_VSSEGSTD)
791: DECLARE_INSN(vssegstb, MATCH_VSSEGSTB, MASK_VSSEGSTB)
792: DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
793: DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X)
794: DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
795: DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM)
796: DECLARE_INSN(vfmsv_s, MATCH_VFMSV_S, MASK_VFMSV_S)
797: DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
798: DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
799: DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
800: DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
801: DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H)
802: DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H)
803: DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
804: DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL)
805: DECLARE_INSN(vfmsv_d, MATCH_VFMSV_D, MASK_VFMSV_D)
806: DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
807: DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
808: DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
809: DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
810: DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
811: DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
812: DECLARE_INSN(vsstw, MATCH_VSSTW, MASK_VSSTW)
813: DECLARE_INSN(vssth, MATCH_VSSTH, MASK_VSSTH)
814: DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
815: DECLARE_INSN(vsstb, MATCH_VSSTB, MASK_VSSTB)
816: DECLARE_INSN(vsstd, MATCH_VSSTD, MASK_VSSTD)
817: DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
818: DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH)
819: DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
820: DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
821: DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
822: DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
823: DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
824: DECLARE_INSN(venqimm1, MATCH_VENQIMM1, MASK_VENQIMM1)
825: DECLARE_INSN(venqimm2, MATCH_VENQIMM2, MASK_VENQIMM2)
826: DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET)
827: DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
828: DECLARE_INSN(vlstw, MATCH_VLSTW, MASK_VLSTW)
829: DECLARE_INSN(vlsth, MATCH_VLSTH, MASK_VLSTH)
830: DECLARE_INSN(vlstb, MATCH_VLSTB, MASK_VLSTB)
831: DECLARE_INSN(vlstd, MATCH_VLSTD, MASK_VLSTD)
832: DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
833: DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
834: DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
835: DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
836: DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
837: DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
838: DECLARE_INSN(vlsegstbu, MATCH_VLSEGSTBU, MASK_VLSEGSTBU)
839: DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
840: DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
841: DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
842: DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
843: DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
844: DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
845: DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H)
846: DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
847: DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
848: DECLARE_INSN(vlstbu, MATCH_VLSTBU, MASK_VLSTBU)
849: DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
850: DECLARE_INSN(flh, MATCH_FLH, MASK_FLH)
851: DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
852: DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
853: DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
854: DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU)
855: DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
856: DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
857: DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
858: DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
859: DECLARE_INSN(vxcptsave, MATCH_VXCPTSAVE, MASK_VXCPTSAVE)
860: DECLARE_INSN(vmsv, MATCH_VMSV, MASK_VMSV)
861: DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
862: DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
863: DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS)
864: DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
865: DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
866: DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H)
867: DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
868: DECLARE_INSN(vxcptkill, MATCH_VXCPTKILL, MASK_VXCPTKILL)
869: DECLARE_INSN(stop, MATCH_STOP, MASK_STOP)
870: DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
871: DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H)
872: DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
873: DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
874: DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
875: DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
876: DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H)
877: DECLARE_INSN(vssegsth, MATCH_VSSEGSTH, MASK_VSSEGSTH)
878: DECLARE_INSN(sw, MATCH_SW, MASK_SW)
879: DECLARE_INSN(vlstwu, MATCH_VLSTWU, MASK_VLSTWU)
880: DECLARE_INSN(vfssegw, MATCH_VFSSEGW, MASK_VFSSEGW)
881: DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
882: DECLARE_INSN(sh, MATCH_SH, MASK_SH)
883: DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H)
884: DECLARE_INSN(vxcptaux, MATCH_VXCPTAUX, MASK_VXCPTAUX)
885: DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
886: DECLARE_INSN(vfssegd, MATCH_VFSSEGD, MASK_VFSSEGD)
887: DECLARE_INSN(vlseghu, MATCH_VLSEGHU, MASK_VLSEGHU)
888: DECLARE_INSN(movn, MATCH_MOVN, MASK_MOVN)
889: DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
890: DECLARE_INSN(vlsthu, MATCH_VLSTHU, MASK_VLSTHU)
891: DECLARE_INSN(movz, MATCH_MOVZ, MASK_MOVZ)
892: DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
893: DECLARE_INSN(ld, MATCH_LD, MASK_LD)
894: DECLARE_INSN(lb, MATCH_LB, MASK_LB)
895: DECLARE_INSN(vlwu, MATCH_VLWU, MASK_VLWU)
896: DECLARE_INSN(lh, MATCH_LH, MASK_LH)
897: DECLARE_INSN(lw, MATCH_LW, MASK_LW)
898: DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
899: DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H)
900: DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
901: DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
902: DECLARE_INSN(vflstd, MATCH_VFLSTD, MASK_VFLSTD)
903: DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
904: DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H)
905: DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR)
906: DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
907: DECLARE_INSN(vflstw, MATCH_VFLSTW, MASK_VFLSTW)
908: DECLARE_INSN(vxcptevac, MATCH_VXCPTEVAC, MASK_VXCPTEVAC)
909: DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
910: DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS)
911: DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
912: DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
913: DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
914: DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
915: DECLARE_INSN(vflsegw, MATCH_VFLSEGW, MASK_VFLSEGW)
916: DECLARE_INSN(c_ld0, MATCH_C_LD0, MASK_C_LD0)
917: DECLARE_INSN(vlsegbu, MATCH_VLSEGBU, MASK_VLSEGBU)
918: DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
919: DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
920: DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
921: DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
922: DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
923: DECLARE_INSN(rem, MATCH_REM, MASK_REM)
924: DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
925: DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
926: DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH)
927: DECLARE_INSN(vlsegsthu, MATCH_VLSEGSTHU, MASK_VLSEGSTHU)
928: DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
929: DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
930: DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H)
931: DECLARE_INSN(vflsegd, MATCH_VFLSEGD, MASK_VFLSEGD)
932: DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
933: DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
934: DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
935: DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H)
936: DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
937: DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
938: DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
939: DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H)
940: DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
941: DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
942: DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
943: DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32)
944: DECLARE_INSN(c_srli32, MATCH_C_SRLI32, MASK_C_SRLI32)
945: DECLARE_INSN(vfsstw, MATCH_VFSSTW, MASK_VFSSTW)
946: DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
947: DECLARE_INSN(c_beq, MATCH_C_BEQ, MASK_C_BEQ)
948: DECLARE_INSN(vfsstd, MATCH_VFSSTD, MASK_VFSSTD)
949: DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
950: DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
951: DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
952: DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU)
953: DECLARE_INSN(vmvv, MATCH_VMVV, MASK_VMVV)
954: DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
955: DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
956: DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
957: DECLARE_INSN(and, MATCH_AND, MASK_AND)
958: DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
959: DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
960: DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
961: DECLARE_INSN(c_sub3, MATCH_C_SUB3, MASK_C_SUB3)
962: DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H)
963: DECLARE_INSN(vlb, MATCH_VLB, MASK_VLB)
964: DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
965: DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
966: DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
967: DECLARE_INSN(vlsegwu, MATCH_VLSEGWU, MASK_VLSEGWU)
968: DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
969: DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
970: DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
971: DECLARE_INSN(vfsw, MATCH_VFSW, MASK_VFSW)
972: DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
973: DECLARE_INSN(sb, MATCH_SB, MASK_SB)
974: DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
975: DECLARE_INSN(vfsd, MATCH_VFSD, MASK_VFSD)
976: DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
977: DECLARE_INSN(sd, MATCH_SD, MASK_SD)
978: DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
979: DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
980: DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
981: DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
982: DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE)
983: DECLARE_INSN(c_bne, MATCH_C_BNE, MASK_C_BNE)
984: DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
985: DECLARE_INSN(vxcptcause, MATCH_VXCPTCAUSE, MASK_VXCPTCAUSE)
986: DECLARE_INSN(vgetcfg, MATCH_VGETCFG, MASK_VGETCFG)
987: DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
988: DECLARE_INSN(vsetcfg, MATCH_VSETCFG, MASK_VSETCFG)
989: DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
990: DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
991: DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H)
992: DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
993: DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
994: DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
995: DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
996: DECLARE_INSN(c_srai32, MATCH_C_SRAI32, MASK_C_SRAI32)
997: DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H)
998: DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
999: DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
1000: DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
1001: DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
1002: DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
1003: DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
1004: DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
1005: DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
1006: DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
1007: DECLARE_INSN(mrts, MATCH_MRTS, MASK_MRTS)
1008: DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
1009: DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
1010: DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
1011: DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H)
1012: DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
1013: DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
1014: DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
1015: DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
1016: DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H)
1017: DECLARE_INSN(venqcnt, MATCH_VENQCNT, MASK_VENQCNT)
1018: DECLARE_INSN(vlbu, MATCH_VLBU, MASK_VLBU)
1019: DECLARE_INSN(vlhu, MATCH_VLHU, MASK_VLHU)
1020: DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
1021: DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
1022: DECLARE_INSN(c_or3, MATCH_C_OR3, MASK_C_OR3)
1023: DECLARE_INSN(c_and3, MATCH_C_AND3, MASK_C_AND3)
1024: DECLARE_INSN(vfssegstw, MATCH_VFSSEGSTW, MASK_VFSSEGSTW)
1025: DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
1026: DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
1027: DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
1028: DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
1029: DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
1030: DECLARE_INSN(vfssegstd, MATCH_VFSSEGSTD, MASK_VFSSEGSTD)
1031: DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
1032: DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
1033: DECLARE_INSN(vf, MATCH_VF, MASK_VF)
1034: DECLARE_INSN(vfmvv, MATCH_VFMVV, MASK_VFMVV)
1035: DECLARE_INSN(vflsegstw, MATCH_VFLSEGSTW, MASK_VFLSEGSTW)
1036: DECLARE_INSN(vxcptrestore, MATCH_VXCPTRESTORE, MASK_VXCPTRESTORE)
1037: DECLARE_INSN(vxcpthold, MATCH_VXCPTHOLD, MASK_VXCPTHOLD)
1038: DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
1039: DECLARE_INSN(vflsegstd, MATCH_VFLSEGSTD, MASK_VFLSEGSTD)
1040: DECLARE_INSN(vfld, MATCH_VFLD, MASK_VFLD)
1041: DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
1042: DECLARE_INSN(vflw, MATCH_VFLW, MASK_VFLW)
1043: DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
1044: DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H)
1045: DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
1046: DECLARE_INSN(vssegw, MATCH_VSSEGW, MASK_VSSEGW)
1047: DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
1048: DECLARE_INSN(vssegh, MATCH_VSSEGH, MASK_VSSEGH)
1049: DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR)
1050: DECLARE_INSN(vssegd, MATCH_VSSEGD, MASK_VSSEGD)
1051: DECLARE_INSN(vssegb, MATCH_VSSEGB, MASK_VSSEGB)
1052: DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H)
1053: DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
1054: DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
1055: DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
1056: DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
1057: DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
1058: DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
1059: DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H)
1060: DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
1061: DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
1062: DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
1063: DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
1064: DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
1065: DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
1066: DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM)
1067: DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
1068: DECLARE_INSN(vsw, MATCH_VSW, MASK_VSW)
1069: DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
1070: DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H)
1071: DECLARE_INSN(vsb, MATCH_VSB, MASK_VSB)
1072: DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
1073: DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI)
1074: DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H)
1075: DECLARE_INSN(vsh, MATCH_VSH, MASK_VSH)
1076: DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
1077: DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S)
1078: DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
1079: DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI)
1080: DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W)
1081: DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L)
1082: DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
1083: DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
1084: DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D)
1085: DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
1086: DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH)
1087: DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
1088: DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
1089: DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
1090: DECLARE_INSN(venqcmd, MATCH_VENQCMD, MASK_VENQCMD)
1091: DECLARE_INSN(or, MATCH_OR, MASK_OR)
1092: DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
1093: DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
1094: DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME)
1095: DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
1096: DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
1097: DECLARE_INSN(c_move, MATCH_C_MOVE, MASK_C_MOVE)
1098: DECLARE_INSN(fmovn, MATCH_FMOVN, MASK_FMOVN)
1099: DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
1100: DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
1101: DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
1102: DECLARE_INSN(fmovz, MATCH_FMOVZ, MASK_FMOVZ)
1103: DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
1104: DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H)
1105: DECLARE_INSN(vsd, MATCH_VSD, MASK_VSD)
1106: DECLARE_INSN(vlsegstw, MATCH_VLSEGSTW, MASK_VLSEGSTW)
1107: DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
1108: DECLARE_INSN(c_slliw, MATCH_C_SLLIW, MASK_C_SLLIW)
1109: DECLARE_INSN(vlsegstb, MATCH_VLSEGSTB, MASK_VLSEGSTB)
1110: DECLARE_INSN(vlsegstd, MATCH_VLSEGSTD, MASK_VLSEGSTD)
1111: DECLARE_INSN(vlsegsth, MATCH_VLSEGSTH, MASK_VLSEGSTH)
1112: DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
1113: DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
1114: DECLARE_INSN(c_slli32, MATCH_C_SLLI32, MASK_C_SLLI32)
1115: DECLARE_INSN(c_add3, MATCH_C_ADD3, MASK_C_ADD3)
1116: DECLARE_INSN(vgetvl, MATCH_VGETVL, MASK_VGETVL)
1117: DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
1118: DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H)
1119: DECLARE_INSN(vlsegb, MATCH_VLSEGB, MASK_VLSEGB)
1120: DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
1121: DECLARE_INSN(vlsegd, MATCH_VLSEGD, MASK_VLSEGD)
1122: DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH)
1123: DECLARE_INSN(vlsegh, MATCH_VLSEGH, MASK_VLSEGH)
1124: DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
1125: DECLARE_INSN(vlsegw, MATCH_VLSEGW, MASK_VLSEGW)
1126: DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
1127: DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
1128: #endif
1129: #ifdef DECLARE_CSR
1130: DECLARE_CSR(fflags, CSR_FFLAGS)
1131: DECLARE_CSR(frm, CSR_FRM)
1132: DECLARE_CSR(fcsr, CSR_FCSR)
1133: DECLARE_CSR(cycle, CSR_CYCLE)
1134: DECLARE_CSR(time, CSR_TIME)
1135: DECLARE_CSR(instret, CSR_INSTRET)
1136: DECLARE_CSR(stats, CSR_STATS)
1137: DECLARE_CSR(uarch0, CSR_UARCH0)
1138: DECLARE_CSR(uarch1, CSR_UARCH1)
1139: DECLARE_CSR(uarch2, CSR_UARCH2)
1140: DECLARE_CSR(uarch3, CSR_UARCH3)
1141: DECLARE_CSR(uarch4, CSR_UARCH4)
1142: DECLARE_CSR(uarch5, CSR_UARCH5)
1143: DECLARE_CSR(uarch6, CSR_UARCH6)
1144: DECLARE_CSR(uarch7, CSR_UARCH7)
1145: DECLARE_CSR(uarch8, CSR_UARCH8)
1146: DECLARE_CSR(uarch9, CSR_UARCH9)
1147: DECLARE_CSR(uarch10, CSR_UARCH10)
1148: DECLARE_CSR(uarch11, CSR_UARCH11)
1149: DECLARE_CSR(uarch12, CSR_UARCH12)
1150: DECLARE_CSR(uarch13, CSR_UARCH13)
1151: DECLARE_CSR(uarch14, CSR_UARCH14)
1152: DECLARE_CSR(uarch15, CSR_UARCH15)
1153: DECLARE_CSR(sstatus, CSR_SSTATUS)
1154: DECLARE_CSR(stvec, CSR_STVEC)
1155: DECLARE_CSR(stimecmp, CSR_STIMECMP)
1156: DECLARE_CSR(sscratch, CSR_SSCRATCH)
1157: DECLARE_CSR(sepc, CSR_SEPC)
1158: DECLARE_CSR(sptbr, CSR_SPTBR)
1159: DECLARE_CSR(sasid, CSR_SASID)
1160: DECLARE_CSR(scycle, CSR_SCYCLE)
1161: DECLARE_CSR(stime, CSR_STIME)
1162: DECLARE_CSR(sinstret, CSR_SINSTRET)
1163: DECLARE_CSR(scause, CSR_SCAUSE)
1164: DECLARE_CSR(sbadaddr, CSR_SBADADDR)
1165: DECLARE_CSR(mstatus, CSR_MSTATUS)
1166: DECLARE_CSR(mscratch, CSR_MSCRATCH)
1167: DECLARE_CSR(mepc, CSR_MEPC)
1168: DECLARE_CSR(mcause, CSR_MCAUSE)
1169: DECLARE_CSR(mbadaddr, CSR_MBADADDR)
1170: DECLARE_CSR(reset, CSR_RESET)
1171: DECLARE_CSR(tohost, CSR_TOHOST)
1172: DECLARE_CSR(fromhost, CSR_FROMHOST)
1173: DECLARE_CSR(send_ipi, CSR_SEND_IPI)
1174: DECLARE_CSR(hartid, CSR_HARTID)
1175: DECLARE_CSR(cycleh, CSR_CYCLEH)
1176: DECLARE_CSR(timeh, CSR_TIMEH)
1177: DECLARE_CSR(instreth, CSR_INSTRETH)
1178: DECLARE_CSR(scycleh, CSR_SCYCLEH)
1179: DECLARE_CSR(stimeh, CSR_STIMEH)
1180: DECLARE_CSR(sinstreth, CSR_SINSTRETH)
1181: #endif
1182: #ifdef DECLARE_CAUSE
1183: DECLARE_CAUSE("fflags", CAUSE_FFLAGS)
1184: DECLARE_CAUSE("frm", CAUSE_FRM)
1185: DECLARE_CAUSE("fcsr", CAUSE_FCSR)
1186: DECLARE_CAUSE("cycle", CAUSE_CYCLE)
1187: DECLARE_CAUSE("time", CAUSE_TIME)
1188: DECLARE_CAUSE("instret", CAUSE_INSTRET)
1189: DECLARE_CAUSE("stats", CAUSE_STATS)
1190: DECLARE_CAUSE("uarch0", CAUSE_UARCH0)
1191: DECLARE_CAUSE("uarch1", CAUSE_UARCH1)
1192: DECLARE_CAUSE("uarch2", CAUSE_UARCH2)
1193: DECLARE_CAUSE("uarch3", CAUSE_UARCH3)
1194: DECLARE_CAUSE("uarch4", CAUSE_UARCH4)
1195: DECLARE_CAUSE("uarch5", CAUSE_UARCH5)
1196: DECLARE_CAUSE("uarch6", CAUSE_UARCH6)
1197: DECLARE_CAUSE("uarch7", CAUSE_UARCH7)
1198: DECLARE_CAUSE("uarch8", CAUSE_UARCH8)
1199: DECLARE_CAUSE("uarch9", CAUSE_UARCH9)
1200: DECLARE_CAUSE("uarch10", CAUSE_UARCH10)
1201: DECLARE_CAUSE("uarch11", CAUSE_UARCH11)
1202: DECLARE_CAUSE("uarch12", CAUSE_UARCH12)
1203: DECLARE_CAUSE("uarch13", CAUSE_UARCH13)
1204: DECLARE_CAUSE("uarch14", CAUSE_UARCH14)
1205: DECLARE_CAUSE("uarch15", CAUSE_UARCH15)
1206: DECLARE_CAUSE("sstatus", CAUSE_SSTATUS)
1207: DECLARE_CAUSE("stvec", CAUSE_STVEC)
1208: DECLARE_CAUSE("stimecmp", CAUSE_STIMECMP)
1209: DECLARE_CAUSE("sscratch", CAUSE_SSCRATCH)
1210: DECLARE_CAUSE("sepc", CAUSE_SEPC)
1211: DECLARE_CAUSE("sptbr", CAUSE_SPTBR)
1212: DECLARE_CAUSE("sasid", CAUSE_SASID)
1213: DECLARE_CAUSE("scycle", CAUSE_SCYCLE)
1214: DECLARE_CAUSE("stime", CAUSE_STIME)
1215: DECLARE_CAUSE("sinstret", CAUSE_SINSTRET)
1216: DECLARE_CAUSE("scause", CAUSE_SCAUSE)
1217: DECLARE_CAUSE("sbadaddr", CAUSE_SBADADDR)
1218: DECLARE_CAUSE("mstatus", CAUSE_MSTATUS)
1219: DECLARE_CAUSE("mscratch", CAUSE_MSCRATCH)
1220: DECLARE_CAUSE("mepc", CAUSE_MEPC)
1221: DECLARE_CAUSE("mcause", CAUSE_MCAUSE)
1222: DECLARE_CAUSE("mbadaddr", CAUSE_MBADADDR)
1223: DECLARE_CAUSE("reset", CAUSE_RESET)
1224: DECLARE_CAUSE("tohost", CAUSE_TOHOST)
1225: DECLARE_CAUSE("fromhost", CAUSE_FROMHOST)
1226: DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI)
1227: DECLARE_CAUSE("hartid", CAUSE_HARTID)
1228: DECLARE_CAUSE("cycleh", CAUSE_CYCLEH)
1229: DECLARE_CAUSE("timeh", CAUSE_TIMEH)
1230: DECLARE_CAUSE("instreth", CAUSE_INSTRETH)
1231: DECLARE_CAUSE("scycleh", CAUSE_SCYCLEH)
1232: DECLARE_CAUSE("stimeh", CAUSE_STIMEH)
1233: DECLARE_CAUSE("sinstreth", CAUSE_SINSTRETH)
1234: #endif
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