Annotation of src/external/gpl3/binutils.old/dist/include/opcode/ppc.h, Revision 1.5.2.1
1.1 christos 1: /* ppc.h -- Header file for PowerPC opcode table
1.5.2.1 ! martin 2: Copyright (C) 1994-2018 Free Software Foundation, Inc.
1.1 christos 3: Written by Ian Lance Taylor, Cygnus Support
4:
5: This file is part of GDB, GAS, and the GNU binutils.
6:
7: GDB, GAS, and the GNU binutils are free software; you can redistribute
8: them and/or modify them under the terms of the GNU General Public
9: License as published by the Free Software Foundation; either version 3,
10: or (at your option) any later version.
11:
12: GDB, GAS, and the GNU binutils are distributed in the hope that they
13: will be useful, but WITHOUT ANY WARRANTY; without even the implied
14: warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15: the GNU General Public License for more details.
16:
17: You should have received a copy of the GNU General Public License
18: along with this file; see the file COPYING3. If not, write to the Free
19: Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20: MA 02110-1301, USA. */
21:
22: #ifndef PPC_H
23: #define PPC_H
24:
25: #include "bfd_stdint.h"
26:
1.5 christos 27: #ifdef __cplusplus
28: extern "C" {
29: #endif
30:
1.1 christos 31: typedef uint64_t ppc_cpu_t;
32:
1.5.2.1 ! martin 33: #if BFD_HOST_64BIT_LONG
! 34: # define PPC_INT_FMT "l"
! 35: #elif defined (__MSVCRT__)
! 36: # define PPC_INT_FMT "I64"
! 37: #else
! 38: # define PPC_INT_FMT "ll"
! 39: #endif
! 40:
1.1 christos 41: /* The opcode table is an array of struct powerpc_opcode. */
42:
43: struct powerpc_opcode
44: {
45: /* The opcode name. */
46: const char *name;
47:
48: /* The opcode itself. Those bits which will be filled in with
49: operands are zeroes. */
1.5.2.1 ! martin 50: uint64_t opcode;
1.1 christos 51:
52: /* The opcode mask. This is used by the disassembler. This is a
53: mask containing ones indicating those bits which must match the
54: opcode field, and zeroes indicating those bits which need not
55: match (and are presumably filled in by operands). */
1.5.2.1 ! martin 56: uint64_t mask;
1.1 christos 57:
58: /* One bit flags for the opcode. These are used to indicate which
59: specific processors support the instructions. The defined values
60: are listed below. */
61: ppc_cpu_t flags;
62:
63: /* One bit flags for the opcode. These are used to indicate which
64: specific processors no longer support the instructions. The defined
65: values are listed below. */
66: ppc_cpu_t deprecated;
67:
68: /* An array of operand codes. Each code is an index into the
69: operand table. They appear in the order which the operands must
70: appear in assembly code, and are terminated by a zero. */
71: unsigned char operands[8];
72: };
73:
74: /* The table itself is sorted by major opcode number, and is otherwise
75: in the order in which the disassembler should consider
76: instructions. */
77: extern const struct powerpc_opcode powerpc_opcodes[];
1.5.2.1 ! martin 78: extern const unsigned int powerpc_num_opcodes;
1.1 christos 79: extern const struct powerpc_opcode vle_opcodes[];
1.5.2.1 ! martin 80: extern const unsigned int vle_num_opcodes;
! 81: extern const struct powerpc_opcode spe2_opcodes[];
! 82: extern const unsigned int spe2_num_opcodes;
1.1 christos 83:
84: /* Values defined for the flags field of a struct powerpc_opcode. */
85:
86: /* Opcode is defined for the PowerPC architecture. */
1.5.2.1 ! martin 87: #define PPC_OPCODE_PPC 0x1ull
1.1 christos 88:
89: /* Opcode is defined for the POWER (RS/6000) architecture. */
1.5.2.1 ! martin 90: #define PPC_OPCODE_POWER 0x2ull
1.1 christos 91:
92: /* Opcode is defined for the POWER2 (Rios 2) architecture. */
1.5.2.1 ! martin 93: #define PPC_OPCODE_POWER2 0x4ull
! 94:
! 95: /* Opcode is only defined on 64 bit architectures. */
! 96: #define PPC_OPCODE_64 0x8ull
1.1 christos 97:
98: /* Opcode is supported by the Motorola PowerPC 601 processor. The 601
99: is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
100: but it also supports many additional POWER instructions. */
1.5.2.1 ! martin 101: #define PPC_OPCODE_601 0x10ull
1.1 christos 102:
103: /* Opcode is supported in both the Power and PowerPC architectures
104: (ie, compiler's -mcpu=common or assembler's -mcom). More than just
105: the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
106: and PPC_OPCODE_POWER2 because many instructions changed mnemonics
107: between POWER and POWERPC. */
1.5.2.1 ! martin 108: #define PPC_OPCODE_COMMON 0x20ull
1.1 christos 109:
110: /* Opcode is supported for any Power or PowerPC platform (this is
111: for the assembler's -many option, and it eliminates duplicates). */
1.5.2.1 ! martin 112: #define PPC_OPCODE_ANY 0x40ull
1.1 christos 113:
114: /* Opcode is supported as part of the 64-bit bridge. */
1.5.2.1 ! martin 115: #define PPC_OPCODE_64_BRIDGE 0x80ull
1.1 christos 116:
117: /* Opcode is supported by Altivec Vector Unit */
1.5.2.1 ! martin 118: #define PPC_OPCODE_ALTIVEC 0x100ull
1.1 christos 119:
120: /* Opcode is supported by PowerPC 403 processor. */
1.5.2.1 ! martin 121: #define PPC_OPCODE_403 0x200ull
1.1 christos 122:
123: /* Opcode is supported by PowerPC BookE processor. */
1.5.2.1 ! martin 124: #define PPC_OPCODE_BOOKE 0x400ull
1.1 christos 125:
126: /* Opcode is only supported by Power4 architecture. */
1.5.2.1 ! martin 127: #define PPC_OPCODE_POWER4 0x800ull
1.1 christos 128:
1.5.2.1 ! martin 129: /* Opcode is only supported by e500x2 Core.
! 130: This bit, PPC_OPCODE_EFS, PPC_OPCODE_VLE, and all those with APU in
! 131: their comment mark opcodes so that when those instructions are used
! 132: an APUinfo entry can be generated. */
! 133: #define PPC_OPCODE_SPE 0x1000ull
1.1 christos 134:
1.5.2.1 ! martin 135: /* Opcode is supported by Integer select APU. */
! 136: #define PPC_OPCODE_ISEL 0x2000ull
1.1 christos 137:
138: /* Opcode is an e500 SPE floating point instruction. */
1.5.2.1 ! martin 139: #define PPC_OPCODE_EFS 0x4000ull
1.1 christos 140:
141: /* Opcode is supported by branch locking APU. */
1.5.2.1 ! martin 142: #define PPC_OPCODE_BRLOCK 0x8000ull
1.1 christos 143:
144: /* Opcode is supported by performance monitor APU. */
1.5.2.1 ! martin 145: #define PPC_OPCODE_PMR 0x10000ull
1.1 christos 146:
147: /* Opcode is supported by cache locking APU. */
1.5.2.1 ! martin 148: #define PPC_OPCODE_CACHELCK 0x20000ull
1.1 christos 149:
150: /* Opcode is supported by machine check APU. */
1.5.2.1 ! martin 151: #define PPC_OPCODE_RFMCI 0x40000ull
! 152:
! 153: /* Opcode is supported by PowerPC 440 processor. */
! 154: #define PPC_OPCODE_440 0x80000ull
1.1 christos 155:
156: /* Opcode is only supported by Power5 architecture. */
1.5.2.1 ! martin 157: #define PPC_OPCODE_POWER5 0x100000ull
1.1 christos 158:
159: /* Opcode is supported by PowerPC e300 family. */
1.5.2.1 ! martin 160: #define PPC_OPCODE_E300 0x200000ull
1.1 christos 161:
162: /* Opcode is only supported by Power6 architecture. */
1.5.2.1 ! martin 163: #define PPC_OPCODE_POWER6 0x400000ull
1.1 christos 164:
165: /* Opcode is only supported by PowerPC Cell family. */
1.5.2.1 ! martin 166: #define PPC_OPCODE_CELL 0x800000ull
1.1 christos 167:
168: /* Opcode is supported by CPUs with paired singles support. */
1.5.2.1 ! martin 169: #define PPC_OPCODE_PPCPS 0x1000000ull
1.1 christos 170:
171: /* Opcode is supported by Power E500MC */
1.5.2.1 ! martin 172: #define PPC_OPCODE_E500MC 0x2000000ull
1.1 christos 173:
174: /* Opcode is supported by PowerPC 405 processor. */
1.5.2.1 ! martin 175: #define PPC_OPCODE_405 0x4000000ull
1.1 christos 176:
177: /* Opcode is supported by Vector-Scalar (VSX) Unit */
1.5.2.1 ! martin 178: #define PPC_OPCODE_VSX 0x8000000ull
! 179:
! 180: /* Opcode is only supported by Power7 architecture. */
! 181: #define PPC_OPCODE_POWER7 0x10000000ull
1.1 christos 182:
183: /* Opcode is supported by A2. */
1.5.2.1 ! martin 184: #define PPC_OPCODE_A2 0x20000000ull
1.1 christos 185:
186: /* Opcode is supported by PowerPC 476 processor. */
1.5.2.1 ! martin 187: #define PPC_OPCODE_476 0x40000000ull
1.1 christos 188:
189: /* Opcode is supported by AppliedMicro Titan core */
1.5.2.1 ! martin 190: #define PPC_OPCODE_TITAN 0x80000000ull
1.1 christos 191:
192: /* Opcode which is supported by the e500 family */
1.5.2.1 ! martin 193: #define PPC_OPCODE_E500 0x100000000ull
1.1 christos 194:
195: /* Opcode is supported by Power E6500 */
1.5.2.1 ! martin 196: #define PPC_OPCODE_E6500 0x200000000ull
1.1 christos 197:
198: /* Opcode is supported by Thread management APU */
1.5.2.1 ! martin 199: #define PPC_OPCODE_TMR 0x400000000ull
1.1 christos 200:
201: /* Opcode which is supported by the VLE extension. */
1.5.2.1 ! martin 202: #define PPC_OPCODE_VLE 0x800000000ull
1.1 christos 203:
1.3 christos 204: /* Opcode is only supported by Power8 architecture. */
1.5.2.1 ! martin 205: #define PPC_OPCODE_POWER8 0x1000000000ull
1.3 christos 206:
207: /* Opcode is supported by ppc750cl. */
1.5.2.1 ! martin 208: #define PPC_OPCODE_750 0x2000000000ull
1.3 christos 209:
210: /* Opcode is supported by ppc7450. */
1.5.2.1 ! martin 211: #define PPC_OPCODE_7450 0x4000000000ull
1.3 christos 212:
213: /* Opcode is supported by ppc821/850/860. */
1.5.2.1 ! martin 214: #define PPC_OPCODE_860 0x8000000000ull
1.3 christos 215:
216: /* Opcode is only supported by Power9 architecture. */
1.5.2.1 ! martin 217: #define PPC_OPCODE_POWER9 0x10000000000ull
! 218:
! 219: /* Opcode is supported by e200z4. */
! 220: #define PPC_OPCODE_E200Z4 0x20000000000ull
! 221:
! 222: /* Disassemble to instructions matching later in the opcode table
! 223: with fewer "mask" bits set rather than the earlist match. Fewer
! 224: "mask" bits set imply a more general form of the opcode, in fact
! 225: the underlying machine instruction. */
! 226: #define PPC_OPCODE_RAW 0x40000000000ull
! 227:
! 228: /* Opcode is supported by PowerPC LSP */
! 229: #define PPC_OPCODE_LSP 0x80000000000ull
! 230:
! 231: /* Opcode is only supported by Freescale SPE2 APU. */
! 232: #define PPC_OPCODE_SPE2 0x100000000000ull
1.3 christos 233:
1.5.2.1 ! martin 234: /* Opcode is supported by EFS2. */
! 235: #define PPC_OPCODE_EFS2 0x200000000000ull
1.3 christos 236:
1.1 christos 237: /* A macro to extract the major opcode from an instruction. */
238: #define PPC_OP(i) (((i) >> 26) & 0x3f)
239:
240: /* A macro to determine if the instruction is a 2-byte VLE insn. */
241: #define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
242:
243: /* A macro to extract the major opcode from a VLE instruction. */
244: #define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
245:
246: /* A macro to convert a VLE opcode to a VLE opcode segment. */
247: #define VLE_OP_TO_SEG(i) ((i) >> 1)
1.5.2.1 ! martin 248:
! 249: /* A macro to extract the extended opcode from a SPE2 instruction. */
! 250: #define SPE2_XOP(i) ((i) & 0x7ff)
! 251:
! 252: /* A macro to convert a SPE2 extended opcode to a SPE2 xopcode segment. */
! 253: #define SPE2_XOP_TO_SEG(i) ((i) >> 7)
1.1 christos 254:
255: /* The operands table is an array of struct powerpc_operand. */
256:
257: struct powerpc_operand
258: {
259: /* A bitmask of bits in the operand. */
1.5.2.1 ! martin 260: uint64_t bitm;
1.1 christos 261:
262: /* The shift operation to be applied to the operand. No shift
263: is made if this is zero. For positive values, the operand
264: is shifted left by SHIFT. For negative values, the operand
265: is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate
266: that BITM and SHIFT cannot be used to determine where the
267: operand goes in the insn. */
268: int shift;
269:
270: /* Insertion function. This is used by the assembler. To insert an
271: operand value into an instruction, check this field.
272:
273: If it is NULL, execute
274: if (o->shift >= 0)
275: i |= (op & o->bitm) << o->shift;
276: else
277: i |= (op & o->bitm) >> -o->shift;
278: (i is the instruction which we are filling in, o is a pointer to
279: this structure, and op is the operand value).
280:
281: If this field is not NULL, then simply call it with the
282: instruction and the operand value. It will return the new value
283: of the instruction. If the ERRMSG argument is not NULL, then if
284: the operand value is illegal, *ERRMSG will be set to a warning
285: string (the operand will be inserted in any case). If the
286: operand value is legal, *ERRMSG will be unchanged (most operands
287: can accept any value). */
1.5.2.1 ! martin 288: uint64_t (*insert)
! 289: (uint64_t instruction, int64_t op, ppc_cpu_t dialect, const char **errmsg);
1.1 christos 290:
291: /* Extraction function. This is used by the disassembler. To
292: extract this operand type from an instruction, check this field.
293:
294: If it is NULL, compute
295: if (o->shift >= 0)
296: op = (i >> o->shift) & o->bitm;
297: else
298: op = (i << -o->shift) & o->bitm;
299: if ((o->flags & PPC_OPERAND_SIGNED) != 0)
300: sign_extend (op);
301: (i is the instruction, o is a pointer to this structure, and op
302: is the result).
303:
304: If this field is not NULL, then simply call it with the
305: instruction value. It will return the value of the operand. If
306: the INVALID argument is not NULL, *INVALID will be set to
307: non-zero if this operand type can not actually be extracted from
308: this operand (i.e., the instruction does not match). If the
309: operand is valid, *INVALID will not be changed. */
1.5.2.1 ! martin 310: int64_t (*extract) (uint64_t instruction, ppc_cpu_t dialect, int *invalid);
1.1 christos 311:
312: /* One bit syntax flags. */
313: unsigned long flags;
314: };
315:
316: /* Elements in the table are retrieved by indexing with values from
317: the operands field of the powerpc_opcodes table. */
318:
319: extern const struct powerpc_operand powerpc_operands[];
320: extern const unsigned int num_powerpc_operands;
321:
322: /* Use with the shift field of a struct powerpc_operand to indicate
323: that BITM and SHIFT cannot be used to determine where the operand
324: goes in the insn. */
1.3 christos 325: #define PPC_OPSHIFT_INV (-1U << 31)
1.1 christos 326:
1.5.2.1 ! martin 327: /* Values defined for the flags field of a struct powerpc_operand.
! 328: Keep the register bits low: They need to fit in an unsigned short. */
1.1 christos 329:
1.5.2.1 ! martin 330: /* This operand names a register. The disassembler uses this to print
! 331: register names with a leading 'r'. */
! 332: #define PPC_OPERAND_GPR (0x1)
1.1 christos 333:
1.5.2.1 ! martin 334: /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
! 335: #define PPC_OPERAND_GPR_0 (0x2)
1.1 christos 336:
1.5.2.1 ! martin 337: /* This operand names a floating point register. The disassembler
! 338: prints these with a leading 'f'. */
! 339: #define PPC_OPERAND_FPR (0x4)
1.1 christos 340:
1.5.2.1 ! martin 341: /* This operand names a vector unit register. The disassembler
! 342: prints these with a leading 'v'. */
! 343: #define PPC_OPERAND_VR (0x8)
1.1 christos 344:
1.5.2.1 ! martin 345: /* This operand names a vector-scalar unit register. The disassembler
! 346: prints these with a leading 'vs'. */
! 347: #define PPC_OPERAND_VSR (0x10)
! 348:
! 349: /* This operand may use the symbolic names for the CR fields (even
! 350: without -mregnames), which are
1.1 christos 351: lt 0 gt 1 eq 2 so 3 un 3
352: cr0 0 cr1 1 cr2 2 cr3 3
353: cr4 4 cr5 5 cr6 6 cr7 7
354: These may be combined arithmetically, as in cr2*4+gt. These are
355: only supported on the PowerPC, not the POWER. */
1.5.2.1 ! martin 356: #define PPC_OPERAND_CR_BIT (0x20)
1.1 christos 357:
1.5.2.1 ! martin 358: /* This is a CR FIELD that does not use symbolic names (unless
! 359: -mregnames is in effect). */
! 360: #define PPC_OPERAND_CR_REG (0x40)
1.1 christos 361:
1.5.2.1 ! martin 362: /* This operand names a special purpose register. */
! 363: #define PPC_OPERAND_SPR (0x80)
1.1 christos 364:
1.5.2.1 ! martin 365: /* This operand names a paired-single graphics quantization register. */
! 366: #define PPC_OPERAND_GQR (0x100)
1.1 christos 367:
368: /* This operand is a relative branch displacement. The disassembler
369: prints these symbolically if possible. */
1.5.2.1 ! martin 370: #define PPC_OPERAND_RELATIVE (0x200)
1.1 christos 371:
372: /* This operand is an absolute branch address. The disassembler
373: prints these symbolically if possible. */
1.5.2.1 ! martin 374: #define PPC_OPERAND_ABSOLUTE (0x400)
! 375:
! 376: /* This operand takes signed values. */
! 377: #define PPC_OPERAND_SIGNED (0x800)
! 378:
! 379: /* This operand takes signed values, but also accepts a full positive
! 380: range of values when running in 32 bit mode. That is, if bits is
! 381: 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
! 382: this flag is ignored. */
! 383: #define PPC_OPERAND_SIGNOPT (0x1000)
! 384:
! 385: /* The next operand should be wrapped in parentheses rather than
! 386: separated from this one by a comma. This is used for the load and
! 387: store instructions which want their operands to look like
! 388: reg,displacement(reg)
! 389: */
! 390: #define PPC_OPERAND_PARENS (0x2000)
! 391:
! 392: /* This operand is for the DS field in a DS form instruction. */
! 393: #define PPC_OPERAND_DS (0x4000)
! 394:
! 395: /* This operand is for the DQ field in a DQ form instruction. */
! 396: #define PPC_OPERAND_DQ (0x8000)
! 397:
! 398: /* This operand should be regarded as a negative number for the
! 399: purposes of overflow checking (i.e., the normal most negative
! 400: number is disallowed and one more than the normal most positive
! 401: number is allowed). This flag will only be set for a signed
! 402: operand. */
! 403: #define PPC_OPERAND_NEGATIVE (0x10000)
! 404:
! 405: /* Valid range of operand is 0..n rather than 0..n-1. */
! 406: #define PPC_OPERAND_PLUS1 (0x20000)
1.1 christos 407:
408: /* This operand is optional, and is zero if omitted. This is used for
409: example, in the optional BF field in the comparison instructions. The
410: assembler must count the number of operands remaining on the line,
411: and the number of operands remaining for the opcode, and decide
412: whether this operand is present or not. The disassembler should
413: print this operand out only if it is not zero. */
1.5.2.1 ! martin 414: #define PPC_OPERAND_OPTIONAL (0x80000)
1.1 christos 415:
416: /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
417: is omitted, then for the next operand use this operand value plus
418: 1, ignoring the next operand field for the opcode. This wretched
419: hack is needed because the Power rotate instructions can take
420: either 4 or 5 operands. The disassembler should print this operand
421: out regardless of the PPC_OPERAND_OPTIONAL field. */
1.5.2.1 ! martin 422: #define PPC_OPERAND_NEXT (0x100000)
1.3 christos 423:
424: /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
425: is omitted, then the value it should use for the operand is stored
426: in the SHIFT field of the immediatly following operand field. */
1.5.2.1 ! martin 427: #define PPC_OPERAND_OPTIONAL_VALUE (0x200000)
! 428:
! 429: /* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is
! 430: only optional when generating 32-bit code. */
! 431: #define PPC_OPERAND_OPTIONAL32 (0x400000)
! 432:
! 433: /* Xilinx APU and FSL related operands */
! 434: #define PPC_OPERAND_FSL (0x800000)
! 435: #define PPC_OPERAND_FCR (0x1000000)
! 436: #define PPC_OPERAND_UDI (0x2000000)
1.1 christos 437:
438: /* The POWER and PowerPC assemblers use a few macros. We keep them
439: with the operands table for simplicity. The macro table is an
440: array of struct powerpc_macro. */
441:
442: struct powerpc_macro
443: {
444: /* The macro name. */
445: const char *name;
446:
447: /* The number of operands the macro takes. */
448: unsigned int operands;
449:
450: /* One bit flags for the opcode. These are used to indicate which
451: specific processors support the instructions. The values are the
452: same as those for the struct powerpc_opcode flags field. */
453: ppc_cpu_t flags;
454:
455: /* A format string to turn the macro into a normal instruction.
456: Each %N in the string is replaced with operand number N (zero
457: based). */
458: const char *format;
459: };
460:
461: extern const struct powerpc_macro powerpc_macros[];
462: extern const int powerpc_num_macros;
463:
464: extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
465:
1.5.2.1 ! martin 466: static inline int64_t
1.3 christos 467: ppc_optional_operand_value (const struct powerpc_operand *operand)
468: {
469: if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
470: return (operand+1)->shift;
471: return 0;
472: }
473:
1.5.2.1 ! martin 474: /* PowerPC VLE insns. */
! 475: /* Form I16L, uses 16A relocs. */
! 476: #define E_OR2I_INSN 0x7000C000
! 477: #define E_AND2I_DOT_INSN 0x7000C800
! 478: #define E_OR2IS_INSN 0x7000D000
! 479: #define E_LIS_INSN 0x7000E000
! 480: #define E_AND2IS_DOT_INSN 0x7000E800
! 481:
! 482: /* Form I16A, uses 16D relocs. */
! 483: #define E_ADD2I_DOT_INSN 0x70008800
! 484: #define E_ADD2IS_INSN 0x70009000
! 485: #define E_CMP16I_INSN 0x70009800
! 486: #define E_MULL2I_INSN 0x7000A000
! 487: #define E_CMPL16I_INSN 0x7000A800
! 488: #define E_CMPH16I_INSN 0x7000B000
! 489: #define E_CMPHL16I_INSN 0x7000B800
! 490:
1.5 christos 491: #ifdef __cplusplus
492: }
493: #endif
494:
1.1 christos 495: #endif /* PPC_H */
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