version 1.4, 2016/12/14 21:48:00 |
version 1.4.8.1, 2018/04/16 01:58:54 |
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@c Copyright (C) 2000-2015 Free Software Foundation, Inc. |
@c Copyright (C) 2000-2016 Free Software Foundation, Inc. |
@c This is part of the GAS manual. |
@c This is part of the GAS manual. |
@c For copying conditions, see the file as.texinfo. |
@c For copying conditions, see the file as.texinfo. |
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Line 64 Assemble for ARC EM. Aliases: @code{-mE |
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Line 64 Assemble for ARC EM. Aliases: @code{-mE |
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@cindex @code{mHS} command line option, ARC |
@cindex @code{mHS} command line option, ARC |
Assemble for ARC HS. Aliases: @code{-mHS}, @code{-mav2hs}. |
Assemble for ARC HS. Aliases: @code{-mHS}, @code{-mav2hs}. |
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@item nps400 |
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@cindex @code{mnps400} command line option, ARC |
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Assemble for ARC 700 with NPS-400 extended instructions. |
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@end table |
@end table |
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Note: the @code{.cpu} directive can to be used to select a core |
Note: the @code{.cpu} directive (@pxref{ARC Directives}) can |
variant from within assembly code. |
to be used to select a core variant from within assembly code. |
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@cindex @code{-EB} command line option, ARC |
@cindex @code{-EB} command line option, ARC |
@item -EB |
@item -EB |
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This option turns on Code Density instructions. Only valid for ARC EM |
This option turns on Code Density instructions. Only valid for ARC EM |
processors. |
processors. |
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@cindex @code{-mrelax} command line option, ARC |
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@item -mrelax |
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Enable support for assembly-time relaxation. The assembler will |
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replace a longer version of an instruction with a shorter one, |
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whenever it is possible. |
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@cindex @code{-mnps400} command line option, ARC |
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@item -mnps400 |
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Enable support for NPS-400 extended instructions. |
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@cindex @code{-mspfp} command line option, ARC |
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@item -mspfp |
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Enable support for single-precision floating point instructions. |
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@cindex @code{-mdpfp} command line option, ARC |
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@item -mdpfp |
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Enable support for double-precision floating point instructions. |
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@cindex @code{-mfpuda} command line option, ARC |
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@item -mfpuda |
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Enable support for double-precision assist floating point instructions. |
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Only valid for ARC EM processors. |
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@end table |
@end table |
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@node ARC Syntax |
@node ARC Syntax |
Line 314 machine directives: |
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Line 341 machine directives: |
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@table @code |
@table @code |
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@cindex @code{lcomm} directive |
@cindex @code{lcomm} directive |
@item .lcomm @var{symbol} , @var{length}[, @var{alignment}] |
@item .lcomm @var{symbol}, @var{length}[, @var{alignment}] |
Reserve @var{length} (an absolute expression) bytes for a local common |
Reserve @var{length} (an absolute expression) bytes for a local common |
denoted by @var{symbol}. The section and value of @var{symbol} are |
denoted by @var{symbol}. The section and value of @var{symbol} are |
those of the new local common. The addresses are allocated in the bss |
those of the new local common. The addresses are allocated in the bss |
Line 329 two. If no alignment is specified, as w |
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Line 356 two. If no alignment is specified, as w |
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largest power of two less than or equal to the size of the symbol, up |
largest power of two less than or equal to the size of the symbol, up |
to a maximum of 16. |
to a maximum of 16. |
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@cindex @code{lcommon} directive |
@cindex @code{lcommon} directive, ARC |
@item .lcommon @var{symbol} , @var{length}[, @var{alignment}] |
@item .lcommon @var{symbol}, @var{length}[, @var{alignment}] |
The same as @code{lcomm} directive. |
The same as @code{lcomm} directive. |
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@cindex @code{cpu} directive, ARC |
@cindex @code{cpu} directive, ARC |
@cindex @code{cpu} directive, ARC |
@item .cpu @var{cpu} |
The @code{.cpu} directive must be followed by the desired core |
The @code{.cpu} directive must be followed by the desired core |
version. Permitted values for CPU are: |
version. Permitted values for CPU are: |
@table @code |
@table @code |
Line 344 Assemble for the ARC600 instruction set. |
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Line 371 Assemble for the ARC600 instruction set. |
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@item ARC700 |
@item ARC700 |
Assemble for the ARC700 instruction set. |
Assemble for the ARC700 instruction set. |
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@item NPS400 |
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Assemble for the NPS400 instruction set. |
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@item EM |
@item EM |
Assemble for the ARC EM instruction set. |
Assemble for the ARC EM instruction set. |
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Line 355 Assemble for the ARC HS instruction set. |
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Line 385 Assemble for the ARC HS instruction set. |
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Note: the @code{.cpu} directive overrides the command line option |
Note: the @code{.cpu} directive overrides the command line option |
@code{-mcpu=@var{cpu}}; a warning is emitted when the version is not |
@code{-mcpu=@var{cpu}}; a warning is emitted when the version is not |
consistent between the two. |
consistent between the two. |
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@item .extAuxRegister @var{name}, @var{addr}, @var{mode} |
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@cindex @code{extAuxRegister} directive, ARC |
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Auxiliary registers can be defined in the assembler source code by |
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using this directive. The first parameter, @var{name}, is the name of the |
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new auxiliary register. The second parameter, @var{addr}, is |
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address the of the auxiliary register. The third parameter, |
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@var{mode}, specifies whether the register is readable and/or writable |
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and is one of: |
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@table @code |
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@item r |
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Read only; |
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@item w |
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Write only; |
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@item r|w |
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Read and write. |
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@end table |
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For example: |
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@example |
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.extAuxRegister mulhi, 0x12, w |
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@end example |
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specifies a write only extension auxiliary register, @var{mulhi} at |
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address 0x12. |
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@item .extCondCode @var{suffix}, @var{val} |
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@cindex @code{extCondCode} directive, ARC |
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ARC supports extensible condition codes. This directive defines a new |
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condition code, to be known by the suffix, @var{suffix} and will |
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depend on the value, @var{val} in the condition code. |
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For example: |
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@example |
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.extCondCode is_busy,0x14 |
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add.is_busy r1,r2,r3 |
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@end example |
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will only execute the @code{add} instruction if the condition code |
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value is 0x14. |
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@item .extCoreRegister @var{name}, @var{regnum}, @var{mode}, @var{shortcut} |
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@cindex @code{extCoreRegister} directive, ARC |
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Specifies an extension core register named @var{name} as a synonym for |
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the register numbered @var{regnum}. The register number must be |
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between 32 and 59. The third argument, @var{mode}, indicates whether |
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the register is readable and/or writable and is one of: |
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@table @code |
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@item r |
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Read only; |
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@item w |
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Write only; |
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@item r|w |
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Read and write. |
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@end table |
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The final parameter, @var{shortcut} indicates whether the register has |
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a short cut in the pipeline. The valid values are: |
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@table @code |
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@item can_shortcut |
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The register has a short cut in the pipeline; |
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@item cannot_shortcut |
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The register does not have a short cut in the pipeline. |
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@end table |
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For example: |
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@example |
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.extCoreRegister mlo, 57, r , can_shortcut |
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@end example |
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defines a read only extension core register, @code{mlo}, which is |
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register 57, and can short cut the pipeline. |
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@item .extInstruction @var{name}, @var{opcode}, @var{subopcode}, @var{suffixclass}, @var{syntaxclass} |
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@cindex @code{extInstruction} directive, ARC |
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ARC allows the user to specify extension instructions. These |
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extension instructions are not macros; the assembler creates encodings |
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for use of these instructions according to the specification by the |
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user. |
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The first argument, @var{name}, gives the name of the instruction. |
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The second argument, @var{opcode}, is the opcode to be used (bits 31:27 |
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in the encoding). |
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The third argument, @var{subopcode}, is the sub-opcode to be used, but |
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the correct value also depends on the fifth argument, |
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@var{syntaxclass} |
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The fourth argument, @var{suffixclass}, determines the kinds of |
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suffixes to be allowed. Valid values are: |
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@table @code |
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@item SUFFIX_NONE |
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No suffixes are permitted; |
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@item SUFFIX_COND |
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Conditional suffixes are permitted; |
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@item SUFFIX_FLAG |
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Flag setting suffixes are permitted. |
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@item SUFFIX_COND|SUFFIX_FLAG |
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Both conditional and flag setting suffices are permitted. |
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@end table |
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The fifth and final argument, @var{syntaxclass}, determines the syntax |
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class for the instruction. It can have the following values: |
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@table @code |
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@item SYNTAX_2OP |
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Two Operand Instruction; |
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@item SYNTAX_3OP |
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Three Operand Instruction. |
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@item SYNTAX_1OP |
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One Operand Instruction. |
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@item SYNTAX_NOP |
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No Operand Instruction. |
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@end table |
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The syntax class may be followed by @samp{|} and one of the following |
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modifiers. |
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@table @code |
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@item OP1_MUST_BE_IMM |
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Modifies syntax class @code{SYNTAX_3OP}, specifying that the first |
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operand of a three-operand instruction must be an immediate (i.e., the |
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result is discarded). This is usually used to set the flags using |
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specific instructions and not retain results. |
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@item OP1_IMM_IMPLIED |
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Modifies syntax class @code{SYNTAX_20P}, specifying that there is an |
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implied immediate destination operand which does not appear in the |
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syntax. |
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For example, if the source code contains an instruction like: |
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@example |
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inst r1,r2 |
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@end example |
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the first argument is an implied immediate (that is, the result is |
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discarded). This is the same as though the source code were: inst |
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0,r1,r2. |
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@end table |
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For example, defining a 64-bit multiplier with immediate operands: |
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@example |
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.extInstruction mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG, |
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SYNTAX_3OP|OP1_MUST_BE_IMM |
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@end example |
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which specifies an extension instruction named @code{mp64} with 3 |
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operands. It sets the flags and can be used with a condition code, |
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for which the first operand is an immediate, i.e. equivalent to |
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discarding the result of the operation. |
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A two operands instruction variant would be: |
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@example |
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.extInstruction mul64, 0x07, 0x2d, SUFFIX_COND, |
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SYNTAX_2OP|OP1_IMM_IMPLIED |
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@end example |
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which describes a two operand instruction with an implicit first |
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immediate operand. The result of this operation would be discarded. |
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@end table |
@end table |
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@node ARC Modifiers |
@node ARC Modifiers |