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Revision 1.5, Tue Aug 11 15:35:17 2020 UTC (2 months, 1 week ago) by maxv
Branch: MAIN
CVS Tags: HEAD
Changes since 1.4: +2 -4 lines

sync

Known issues in NVMM, low priority in most cases.

====== KERNEL NVMM DRIVER ======

 * 32bit-PAE guests can misbehave on Intel, because we need to manually
   install the PDPTEs, and currently we don't do it. In practice they don't
   misbehave because the emulator never has to interfere with CR3.

 * AMD: we don't support VCPU_CONF_TPR, would be nice to.

 * AMD: need to do comprehensive CPUID filtering, like we already do on
   Intel.

====== LIBNVMM ======

 * There are still a few twisted corner cases we don't handle in the instruction
   emulator. For example if the guest makes an MMIO access relative to RSP, we
   must base the GVA on %SS and not %DS. This is tiring, and in practice, no
   guest is dumb enough to perform such accesses.

 * Maybe the __areas should have a rwlock? I don't think Qemu unmaps memory
   while VCPUs are running, but still.