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Diff for /src/common/lib/libc/arch/mips/atomic/membar_ops.S between version 1.12 and 1.13

version 1.12, 2022/04/09 23:32:51 version 1.13, 2022/04/21 12:06:31
Line 38  LEAF(_membar_sync)
Line 38  LEAF(_membar_sync)
         j       ra          j       ra
          BDSYNC           BDSYNC
 END(_membar_sync)  END(_membar_sync)
   ATOMIC_OP_ALIAS(membar_sync,_membar_sync)
   
   STRONG_ALIAS(_membar_enter,_membar_sync)
   ATOMIC_OP_ALIAS(membar_enter,_membar_sync)
   
 #ifdef __OCTEON__  #ifdef __OCTEON__
   
   /*
    * cnMIPS guarantees load-before-load/store ordering without any
    * barriers.  So the only barriers we need are store-before-load (sync)
    * and store-before-store (syncw, i.e., sync 4).  See Table 2-32
    * `Execution Ordering Rules' on p. 104 of Cavium OCTEON III CN78XX
    * Hardware Reference Manual, CN78XX-HM-0.99E, September 2014:
    *
    *      First Operation         DLD [load instruction to a physical
    *                              address that is L2/DRAM]
    *      Second Operation        Any
    *      Execution Ordering Comments
    *
    *              The second operation cannot appear to execute before
    *              the first (DLD) operation, regardless of the presence
    *              or absence of SYNC* instructions.
    *
    * Note: I'm not sure if this applies to earlier cnMIPS -- can't find
    * it in the Cavium Networks OCTEON Plus CN50XX Hardware Reference
    * Manual CN50XX-HM-0.99E, July 2008.  Experimentally, on an erlite3
    * (Cavium Octeon CN5020-500), I can easily detect reordering of
    * store-before-store and store-before-load, but I haven't been able to
    * detect any reordering of load-before-load or load-before-store.
    *
    * Note: On early cnMIPS (CN3xxx), there is an erratum which sometimes
    * requires issuing two syncw's in a row.  I don't know the details --
    * don't have documentation -- and in Linux it is only used for I/O
    * purposes.
    *
    * Currently we don't build kernels that work on both Octeon and
    * non-Octeon MIPS CPUs, so none of this is done with binary patching.
    * For userlands we could use a separate shared library on Octeon with
    * ld.so.conf to override the symbols with cheaper definitions, but we
    * don't do that now.
    */
   
   LEAF(_membar_acquire)
           j       ra
            nop
   END(_membar_acquire)
   ATOMIC_OP_ALIAS(membar_acquire,_membar_acquire)
   
   STRONG_ALIAS(_membar_consumer,_membar_acquire)
   ATOMIC_OP_ALIAS(membar_consumer,_membar_acquire)
   
 LEAF(_membar_release)  LEAF(_membar_release)
         /*  
          * syncw is documented as ordering store-before-store in  
          *  
          *      Cavium OCTEON III CN78XX Hardware Reference Manual,  
          *      CN78XX-HM-0.99E, September 2014.  
          *  
          * It's unclear from the documentation the architecture  
          * guarantees load-before-store ordering without barriers, but  
          * this code assumes it does.  If that assumption is wrong, we  
          * can only use syncw for membar_producer -- membar_release has  
          * to use the full sync.  
          */  
         j       ra          j       ra
          syncw           syncw
 END(_membar_release)  END(_membar_release)
 #endif  ATOMIC_OP_ALIAS(membar_release,_membar_release)
   
 ATOMIC_OP_ALIAS(membar_sync,_membar_sync)  
 ATOMIC_OP_ALIAS(membar_acquire,_membar_sync)  
 STRONG_ALIAS(_membar_acquire,_membar_sync)  
 ATOMIC_OP_ALIAS(membar_enter,_membar_sync)  
 STRONG_ALIAS(_membar_enter,_membar_sync)  
 #ifdef __OCTEON__  
 ATOMIC_OP_ALIAS(membar_exit,_membar_release)  
 STRONG_ALIAS(_membar_exit,_membar_release)  STRONG_ALIAS(_membar_exit,_membar_release)
 ATOMIC_OP_ALIAS(membar_release,_membar_release)  ATOMIC_OP_ALIAS(membar_exit,_membar_release)
 ATOMIC_OP_ALIAS(membar_producer,_membar_release)  
 STRONG_ALIAS(_membar_producer,_membar_release)  STRONG_ALIAS(_membar_producer,_membar_release)
 #else  ATOMIC_OP_ALIAS(membar_producer,_membar_release)
 ATOMIC_OP_ALIAS(membar_exit,_membar_sync)  
 STRONG_ALIAS(_membar_exit,_membar_sync)  #else  /* !__OCTEON__ */
 ATOMIC_OP_ALIAS(membar_release,_membar_sync)  
   STRONG_ALIAS(_membar_acquire,_membar_sync)
   ATOMIC_OP_ALIAS(membar_acquire,_membar_sync)
 STRONG_ALIAS(_membar_release,_membar_sync)  STRONG_ALIAS(_membar_release,_membar_sync)
 ATOMIC_OP_ALIAS(membar_producer,_membar_sync)  ATOMIC_OP_ALIAS(membar_release,_membar_sync)
   STRONG_ALIAS(_membar_exit,_membar_sync)
   ATOMIC_OP_ALIAS(membar_exit,_membar_sync)
   STRONG_ALIAS(_membar_consumer,_membar_sync)
   ATOMIC_OP_ALIAS(membar_consumer,_membar_sync)
 STRONG_ALIAS(_membar_producer,_membar_sync)  STRONG_ALIAS(_membar_producer,_membar_sync)
   ATOMIC_OP_ALIAS(membar_producer,_membar_sync)
   
 #endif  #endif
 ATOMIC_OP_ALIAS(membar_consumer,_membar_sync)  
 STRONG_ALIAS(_membar_consumer,_membar_sync)  
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  Added in v.1.13
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