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Pull up following revision(s) (requested by skrll in ticket #1330):
common/lib/libc/arch/arm/atomic/atomic_swap.S: revision 1.18
common/lib/libc/arch/arm/atomic/atomic_and_16.S: revision 1.5
common/lib/libc/arch/arm/atomic/atomic_swap.S: revision 1.19
common/lib/libc/arch/arm/atomic/atomic_xor_64.S: revision 1.6
common/lib/libc/arch/arm/atomic/atomic_inc_32.S: revision 1.8
common/lib/libc/arch/arm/atomic/atomic_and_32.S: revision 1.9
common/lib/libc/arch/arm/atomic/atomic_add_8.S: revision 1.4
common/lib/libc/arch/arm/atomic/atomic_xor_64.S: revision 1.7
common/lib/libc/arch/arm/atomic/atomic_inc_32.S: revision 1.9
common/lib/libc/arch/arm/atomic/atomic_cas_up.S: revision 1.8
common/lib/libc/arch/arm/atomic/atomic_add_8.S: revision 1.5
common/lib/libc/arch/arm/atomic/atomic_op_asm.h: revision 1.9
common/lib/libc/arch/arm/atomic/membar_ops.S: revision 1.8
common/lib/libc/arch/arm/atomic/membar_ops.S: revision 1.9
common/lib/libc/arch/arm/atomic/atomic_op_asm.h: revision 1.10
common/lib/libc/arch/arm/atomic/atomic_and_32.S: revision 1.10
common/lib/libc/arch/arm/atomic/atomic_cas_16.S: revision 1.3
common/lib/libc/arch/arm/atomic/sync_fetch_and_and_8.S: revision 1.6
common/lib/libc/arch/arm/atomic/atomic_xor_32.S: revision 1.4
common/lib/libc/arch/arm/atomic/atomic_xor_32.S: revision 1.5
common/lib/libc/arch/arm/atomic/atomic_nand_64.S: revision 1.6
common/lib/libc/arch/arm/atomic/atomic_xor_16.S: revision 1.4
common/lib/libc/arch/arm/atomic/atomic_swap_16.S: revision 1.6
common/lib/libc/arch/arm/atomic/atomic_nand_64.S: revision 1.7
common/lib/libc/arch/arm/atomic/atomic_cas_32.S: revision 1.8
common/lib/libc/arch/arm/atomic/atomic_xor_16.S: revision 1.5
common/lib/libc/arch/arm/atomic/atomic_swap_16.S: revision 1.7
common/lib/libc/arch/arm/atomic/atomic_add_32.S: revision 1.10
common/lib/libc/arch/arm/atomic/sync_fetch_and_add_8.S: revision 1.6
common/lib/libc/arch/arm/atomic/atomic_dec_64.S: revision 1.8
common/lib/libc/arch/arm/atomic/atomic_add_16.S: revision 1.4
common/lib/libc/arch/arm/atomic/sync_fetch_and_sub_8.S: revision 1.6
common/lib/libc/arch/arm/atomic/atomic_xor_8.S: revision 1.4
common/lib/libc/arch/arm/atomic/atomic_dec_64.S: revision 1.9
common/lib/libc/arch/arm/atomic/atomic_add_16.S: revision 1.5
common/lib/libc/arch/arm/atomic/atomic_xor_8.S: revision 1.5
common/lib/libc/arch/arm/atomic/atomic_or_64.S: revision 1.13
common/lib/libc/arch/arm/atomic/atomic_add_32.S: revision 1.9
common/lib/libc/arch/arm/atomic/atomic_or_64.S: revision 1.14
common/lib/libc/arch/arm/atomic/atomic_or_16.S: revision 1.4
common/lib/libc/arch/arm/atomic/atomic_or_16.S: revision 1.5
common/lib/libc/arch/arm/atomic/sync_fetch_and_nand_8.S: revision 1.6
common/lib/libc/arch/arm/atomic/atomic_nand_16.S: revision 1.4
common/lib/libc/arch/arm/atomic/atomic_nand_16.S: revision 1.5
common/lib/libc/arch/arm/atomic/sync_fetch_and_or_8.S: revision 1.6
common/lib/libc/arch/arm/atomic/atomic_nand_32.S: revision 1.4
common/lib/libc/arch/arm/atomic/atomic_or_32.S: revision 1.9
common/lib/libc/arch/arm/atomic/atomic_nand_32.S: revision 1.5
common/lib/libc/arch/arm/atomic/atomic_cas_8.S: revision 1.9
common/lib/libc/arch/arm/atomic/atomic_inc_64.S: revision 1.10
common/lib/libc/arch/arm/atomic/atomic_inc_64.S: revision 1.11
common/lib/libc/arch/arm/atomic/atomic_cas_64.S: revision 1.12
common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_8.S: revision 1.5
common/lib/libc/arch/arm/atomic/atomic_or_8.S: revision 1.4
common/lib/libc/arch/arm/atomic/atomic_dec_32.S: revision 1.6
common/lib/libc/arch/arm/atomic/atomic_or_8.S: revision 1.5
common/lib/libc/arch/arm/atomic/atomic_dec_32.S: revision 1.7
common/lib/libc/arch/arm/atomic/atomic_sub_64.S: revision 1.4
common/lib/libc/arch/arm/atomic/atomic_sub_64.S: revision 1.5
common/lib/libc/arch/arm/atomic/sync_fetch_and_xor_8.S: revision 1.6
common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_4.S: revision 1.4
common/lib/libc/arch/arm/atomic/atomic_and_64.S: revision 1.12
common/lib/libc/arch/arm/atomic/atomic_or_32.S: revision 1.10
common/lib/libc/arch/arm/atomic/atomic_and_64.S: revision 1.13
common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_2.S: revision 1.4
common/lib/libc/arch/arm/atomic/atomic_swap_64.S: revision 1.14
common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_1.S: revision 1.4
common/lib/libc/arch/arm/atomic/atomic_nand_8.S: revision 1.4
common/lib/libc/arch/arm/atomic/atomic_and_8.S: revision 1.4
common/lib/libc/arch/arm/atomic/atomic_add_64.S: revision 1.13
common/lib/libc/arch/arm/atomic/atomic_nand_8.S: revision 1.5
common/lib/libc/arch/arm/atomic/atomic_and_8.S: revision 1.5
common/lib/libc/arch/arm/atomic/atomic_and_16.S: revision 1.4
common/lib/libc/arch/arm/atomic/atomic_add_64.S: revision 1.14
Give the thumb atomic ops a chance of working
s/ifdef _ARM_ARCH_6/if defined(_ARM_ARCH_6)/ for consistency. NFCI.
Remove memory barriers from the atomic_ops(3) atomic operations. They're
not needed for correctness.
Add the correct memory barriers to the gcc legacy __sync built-in
functions for atomic memory access. From the gcc documentation:
In most cases, these built-in functions are considered a full barrier.
That is, no memory operand is moved across the operation, either forward
or backward. Further, instructions are issued as necessary to prevent the
processor from speculating loads across the operation and from queuing
stores after the operation.
type __sync_lock_test_and_set (type *ptr, type value, ...)
This built-in function is not a full barrier, but rather an acquire
barrier. This means that references after the operation cannot move to
(or be speculated to) before the operation, but previous memory stores
may not be globally visible yet, and previous memory loads may not yet
be satisfied.
void __sync_lock_release (type *ptr, ...)
This built-in function is not a full barrier, but rather a release
barrier. This means that all previous memory stores are globally
visible, and all previous memory loads have been satisfied, but
following memory reads are not prevented from being speculated to
before the barrier.
Remove memory barriers from the atomic_ops(3) atomic operations. They're not needed for correctness. Add the correct memory barriers to the gcc legacy __sync built-in functions for atomic memory access. From the gcc documentation: In most cases, these built-in functions are considered a full barrier. That is, no memory operand is moved across the operation, either forward or backward. Further, instructions are issued as necessary to prevent the processor from speculating loads across the operation and from queuing stores after the operation. type __sync_lock_test_and_set (type *ptr, type value, ...) This built-in function is not a full barrier, but rather an acquire barrier. This means that references after the operation cannot move to (or be speculated to) before the operation, but previous memory stores may not be globally visible yet, and previous memory loads may not yet be satisfied. void __sync_lock_release (type *ptr, ...) This built-in function is not a full barrier, but rather a release barrier. This means that all previous memory stores are globally visible, and all previous memory loads have been satisfied, but following memory reads are not prevented from being speculated to before the barrier.
s/ifdef _ARM_ARCH_6/if defined(_ARM_ARCH_6)/ for consistency. NFCI.
Pull up following revision(s) (requested by skrll in ticket #1313): common/lib/libc/arch/arm/atomic/atomic_xor_64.S: revision 1.5 common/lib/libc/arch/arm/atomic/atomic_nand_64.S: revision 1.5 common/lib/libc/arch/arm/atomic/atomic_or_64.S: revision 1.12 common/lib/libc/arch/arm/atomic/atomic_cas_8.S: revision 1.8 common/lib/libc/arch/arm/atomic/atomic_sub_64.S: revision 1.3 common/lib/libc/arch/arm/atomic/atomic_and_64.S: revision 1.11 common/lib/libc/arch/arm/atomic/atomic_swap_64.S: revision 1.13 common/lib/libc/arch/arm/atomic/atomic_add_64.S: revision 1.12 Whitespace
Whitespace
Sync with HEAD
Mostly merge changes from HEAD upto 20200411
Pull up following revision(s) (requested by skrll in ticket #202):
common/lib/libc/arch/arm/atomic/atomic_xor_64.S: revision 1.4
common/lib/libc/arch/arm/atomic/atomic_or_64.S: revision 1.11
__sync_{,x}or_and_fetch_8 should return new value... make it so.
Pull up following revision(s) (requested by skrll in ticket #1375):
common/lib/libc/arch/arm/atomic/atomic_xor_64.S: revision 1.4
common/lib/libc/arch/arm/atomic/atomic_or_64.S: revision 1.11
__sync_{,x}or_and_fetch_8 should return new value... make it so.
__sync_{,x}or_and_fetch_8 should return new value... make it so.
Rebase to HEAD as of a few days ago.
sync with head.
for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.
this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
file atomic_xor_64.S was added on branch tls-maxphys on 2014-08-19 23:45:12 +0000
file atomic_xor_64.S was added on branch yamt-pagecache on 2014-05-22 11:26:28 +0000
Don't export __sync* if _KERNEL || _STANDALONE are defined. (except if _RUMPKERNEL is defined)
Use explicit form of register pair operations by specifying both.
Add support for the gcc __sync builtins. Note that these need earmv6 or later to get the ldrex/strex instructions