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aarch64: Implement __aarch64_casN_sync.

gcc generates calls to this symbol in programs that use
__sync_*_compare_and_swap, which require full sequential consistency
barriers, including store-before-load ordering on both sides of the
atomic; none of the release/acquire operations guarantee that, so we
have to insert explicit DMB instructions.

Note: gcc's own definition omits some of the DMB instructions, but I
can't prove that it's correct that way -- stores preceding the CAS
must complete before the load part of the CAS, and the store part of
the CAS must complete before loads following the CAS.  Maybe there's
some way to prove that one of these orderings is guaranteed some
other way than a DMB but I'm not seeing it, and store-before-load
ordering is hard to understand.

Patch by skrll@ based on a patch by mrg@, soliloquy in commit message
by me.

Provide all the LSE operation fuctions.  The use of LSE instructions is
currently disabled.

Do previous differently as the API is different.

Provide some more operations that are part of compiler lse.S.  This is
incomplete, but at least covers all the atomic_swap ops and allows the
aa64 kernel to link with gcc 10.

Ooops, restore accidently removed files from merge mishap

Sync with HEAD

Rebase to HEAD as of a few days ago.

file Makefile.inc was added on branch tls-maxphys on 2014-08-19 23:45:11 +0000

Preliminary files for AARCH64 (64-bit ARM) support.
Enough for a distribution build.