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CVS log for pkgsrc/devel/capstone/distinfo

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Default branch: MAIN

Revision 1.13 / (download) - annotate - [select for diffs], Tue Aug 18 20:20:46 2020 UTC (4 weeks, 5 days ago) by riastradh
Branch: MAIN
Changes since 1.12: +8 -8 lines
Diff to previous 1.12 (colored)

devel/capstone: Update to 4.0.2

July 18, 2018

Release 3.0.5 is a stable release version, with important fixes in the core & several bindings against v3.0.5-rc3.

    Fix the include path for Android builds when building cstool.
    Add posibility to disable universal build for Mac OS.
    cstool: Separate instruction bytes by spaces.
    Fix code path of pkg-config in Cmake.
    Update XCode project for XCode 9.1.
    Add Cortex-M support to cstool.
    Cmake forces to be build using MT with MSVC.
    Better support for Mac OS kernel.


    Fix some issues in handling EVEX & VEX3 instructions.
    Fix immediate operand for AND instruction in ATT mode.
    Fix ATT syntax when imm operand is 0.
    Better handle XACQUIRE/XRELEASE.
    Fix imm operand of RETF.


    Fix an integer overlow bug.


    Bug fix for incorrect operand type in certain load/store instructions.


    Mode CS_MODE_MIPS32R6 automatically sets CS_MODE_32


    Fix endian check.


    Fix an integer overlow bug.


    Fix an integer overlow bug.

Python binding

    Raise error on accessing irrelevant data fields if skipdata & detail modes are enable.

December 18, 2018

Release 4.0 is a stable release version, with important fixes in the core & several bindings against v3.0.5.

    New APIs: cs_regs_access()
    Add new options for cs_option(): CS_OPT_MNEMONIC & CS_OPT_UNSIGNED & CS_OPT_SYNTAX_MASM.
    Various updates & bugfixes for all architectures.
    Add 4 new architectures: EVM, M68K, M680X & TMS320C64x.
    Add new error types: CS_ERR_X86_MASM.


    Add XOP code condition type in x86_xop_cc.
    Add some info on encoding to cs_x86 in cs_x86_encoding.
    Add register flags update in cs_x86.{eflags, fpu_flags}
    Change cs_x86.disp type from int32_t to int64_t.
    Add new groups: X86_GRP_VM & X86_GRP_FPU.
    Lots of new instructions (AVX)


    Add instruction ARM64_INS_NEGS & ARM64_INS_NGCS.


    Add mode CS_MODE_MIPS2.


    Change cs_ppc_op.imm type from int32_t to int64_t.
    Lots of new instructions (QPX among them)


    Change cs_sparc_op.imm type from int32_t to int64_t.


    New bindings: PowerShell & VB6

January 10, 2019

Release 4.0.1 is a stable release version, with minor bugfixes in the core & Python binding.

    Fix some issues for packaging (Debian, Gentoo, etc).
    Better support for building with Mingw.
    cstool has new option -s to turn on skipdata mode.
    cstool -v now report build settings of the core.
    Add suite/capstone_get_setup.c so users can integrate with their own code to retrieve Capstone settings at build time.


    Fix 4.0 regression: the tbh [r0, r1, lsl #1] instruction sets the operand.shift.value back again.
    Remove ARM_REG_PC group for BX instruction.


    endbr32 and endbr64 instructions are now properly decoded in both CS_MODE_32 and CS_MODE_64.


    Fix some issues reported by clang-analyzer.

Python binding

    Fix skipdata setup.
    Add getter/setter for skipdata_mnem & skipdata_callback.

May 8, 2020

Release 4.0.2 is a stable release version, with minor bugfixes in the core & some bindings.

    Windows kernel-mode driver support
    Fix installation path on FreeBSD and DragonFly


    Add armv8, ppc32 & thumbv8 modes
    Print instruction ID


    Support CS_OPT_UNSIGNED for ATT syntax
    Fix operand size for some instructions
    Fix LOCK prefixes
    Recognize xacquire/xrelease prefix
    Fix call/jmp access mode of mem operand
    Add ENDBR32, ENDBR64 to reduce mode
    Other minor fixes


    Update writeback for STR_POST_REG


    Fix register access flags for memory instructions
    Fix UMOV vess


    Store correct register value in op.reg_pair


    BDZLA is absolute branch


    Fix truncated 64bit imm operand
    Fix base/index printing

Python binding

    Fix skipdata struct being destroyed
    Add repr for capstone.CsInsn

Java binding

    Fix Java bindings to use pointers instead of longs

Ocaml binding

    Fix x86_op record

Revision 1.12 / (download) - annotate - [select for diffs], Sat Aug 25 14:39:11 2018 UTC (2 years ago) by wiz
Branch: MAIN
CVS Tags: pkgsrc-2020Q2-base, pkgsrc-2020Q2, pkgsrc-2020Q1-base, pkgsrc-2020Q1, pkgsrc-2019Q4-base, pkgsrc-2019Q4, pkgsrc-2019Q3-base, pkgsrc-2019Q3, pkgsrc-2019Q2-base, pkgsrc-2019Q2, pkgsrc-2019Q1-base, pkgsrc-2019Q1, pkgsrc-2018Q4-base, pkgsrc-2018Q4, pkgsrc-2018Q3-base, pkgsrc-2018Q3
Changes since 1.11: +2 -2 lines
Diff to previous 1.11 (colored)

capstone: honor LDFLAGS for cstool.

Fixes RELRO build.

Revision 1.11 / (download) - annotate - [select for diffs], Sat Mar 24 17:10:42 2018 UTC (2 years, 5 months ago) by joerg
Branch: MAIN
CVS Tags: pkgsrc-2018Q2-base, pkgsrc-2018Q2, pkgsrc-2018Q1-base, pkgsrc-2018Q1
Changes since 1.10: +3 -1 lines
Diff to previous 1.10 (colored)

Don't build capstone locally in the Python binding.

Revision 1.10 / (download) - annotate - [select for diffs], Fri Feb 23 02:42:06 2018 UTC (2 years, 6 months ago) by khorben
Branch: MAIN
Changes since 1.9: +6 -6 lines
Diff to previous 1.9 (colored)

Update devel/capstone to version 3.0.5-rc2

This provides important fixes in the core & several bindings:


    Fix build for Visual Studio 2012
    Fix X86_REL_ADDR macro
    Better support for embedding Capstone into Windows kernel drivers
    Support to embedded Capstone into MacOS kernel
    Support MacOS 10.11 and up
    Better support for Cygwin
    Support build packages for FreeBSD & DragonflyBSD
    Add a command-line tool "cstool"
    Properly handle switching to Endian mode at run-time for Arm, Arm64, Mips & Sparc


    Some random 16-bit code can be handled wrongly.
    Remove abundant operand type X86_OP_FP
    Add X86_REG_EFLAGS for STC and STD
    Fix instruction attributes for SYSEXIT, MOVW, ROL, LGS, SLDT
    Rename registers ST0-ST7 to be consistent with asm output


    Properly handle IT instruction
    Fix LDRSB
    Fix writeback for LDR
    Fix Thumb BigEndian setup


    Fix arith extender
    Fix writeback for LDR
    Rename enum arm64_mrs_reg to arm64_sysreg


    Print 0 offset for memory operand


    Fix POPC instruction

Python binding

    Better PyPy support
    Add __version__
    Better support for Python 3
    Fix CS_SKIPDATA_CALLBACK prototype
    Cast skipdata function inside binding to simplify the API

Java binding

    Better handle input with invalid code

PowerShell binding

    New binding

Build-tested with devel/ropper and devel/{py-,}radare2 on NetBSD/amd64.

Revision 1.9 / (download) - annotate - [select for diffs], Sat Feb 20 11:40:30 2016 UTC (4 years, 7 months ago) by jperkin
Branch: MAIN
CVS Tags: pkgsrc-2017Q4-base, pkgsrc-2017Q4, pkgsrc-2017Q3-base, pkgsrc-2017Q3, pkgsrc-2017Q2-base, pkgsrc-2017Q2, pkgsrc-2017Q1-base, pkgsrc-2017Q1, pkgsrc-2016Q4-base, pkgsrc-2016Q4, pkgsrc-2016Q3-base, pkgsrc-2016Q3, pkgsrc-2016Q2-base, pkgsrc-2016Q2, pkgsrc-2016Q1-base, pkgsrc-2016Q1
Changes since 1.8: +2 -2 lines
Diff to previous 1.8 (colored)

Fix install_name on Darwin.  Bump PKGREVISION.

Revision 1.8 / (download) - annotate - [select for diffs], Tue Nov 3 03:27:17 2015 UTC (4 years, 10 months ago) by agc
Branch: MAIN
CVS Tags: pkgsrc-2015Q4-base, pkgsrc-2015Q4
Changes since 1.7: +2 -1 lines
Diff to previous 1.7 (colored)

Add SHA512 digests for distfiles for devel category

Issues found with existing distfiles:
No changes made to these distinfo files.

Otherwise, existing SHA1 digests verified and found to be the same on
the machine holding the existing distfiles (morden).  All existing
SHA1 digests retained for now as an audit trail.

Revision 1.7 / (download) - annotate - [select for diffs], Tue Jul 28 12:48:14 2015 UTC (5 years, 1 month ago) by sevan
Branch: MAIN
CVS Tags: pkgsrc-2015Q3-base, pkgsrc-2015Q3
Changes since 1.6: +2 -1 lines
Diff to previous 1.6 (colored)

"Backport upstream patch for pkgsrc to unbreak FreeBSD and DragonflyBSD" - kamil@

Revision 1.6 / (download) - annotate - [select for diffs], Sun Jul 19 14:49:44 2015 UTC (5 years, 2 months ago) by kamil
Branch: MAIN
Changes since 1.5: +4 -4 lines
Diff to previous 1.5 (colored)

Update to 3.0.4
Version 3.0.4: Jul 16th, 2015

    Improve cross-compile for Android using Android NDK.
    Support cross-compile for AArch64 Android (with Linux GCC).
    Removed osxkernel_inttypes.h due to license issue (incompatible with BSD license).
    Now it is possible to compile with CC having a space inside (such as "ccache gcc")

    Fix a null pointer dereference bug on handling code with special prefixes.
    Properly handle AL/AX/EAX operand for OUT instruction in AT&T syntax.
    Print immediate operand in positive form in some algorithm instructions.
    Properly decode some SSE instructions.

    Fixed some memory corruption bugs.

    Fixed instruction ID of SUBU instruction.
    Fixed a memory corruption bug.

    Fixed a memory corruption bug on IT instruction.

    Fixed a memory corruption bug when instruction has a memory operand.

    Support Virtualenv. supports option --user if not in a virtualenv to allow for local usage.
    Properly handle the destruction of Cs object in the case the shared library was already unloaded.

Revision 1.5 / (download) - annotate - [select for diffs], Sat May 9 07:00:08 2015 UTC (5 years, 4 months ago) by mef
Branch: MAIN
CVS Tags: pkgsrc-2015Q2-base, pkgsrc-2015Q2
Changes since 1.4: +4 -4 lines
Diff to previous 1.4 (colored)

Update to 3.0.3
Version 3.0.3: May 08th, 2015
[ Library ]

- Support to embed into Mac OS X kernel extensions.
- Now it is possible to compile Capstone with older C compilers, such as
  GCC 4.8 on Ubuntu 12.04.
- Add "test_iter" to MSVC project.

[ X86 ]
- All shifted instructions SHL, SHR, SAL, SAR, RCL, RCR, ROL & ROR now support
  $1 as first operand in *AT&T* syntax (so we have "rcll $1, %edx" instead of
  "rcll %edx").
- CMPXCHG16B is a valid instruction with LOCK prefix.
- Fixed a segfault on the input of 0xF3.

[ Arm ]
- BLX instruction modifies PC & LR registers.

[ Sparc ]
- Improved displacement decoding for sparc banching instructions.

[ Python binding ]
- Fix for Cython so it can properly initialize.
- X86Op.avx_zero_mask now has c_bool type, but not c_uint8 type.
- Properly support compile with Cygwin & install binding (

Revision 1.4 / (download) - annotate - [select for diffs], Sat May 9 06:57:25 2015 UTC (5 years, 4 months ago) by mef
Branch: MAIN
Changes since 1.3: +4 -4 lines
Diff to previous 1.3 (colored)

Githubify. Binary may not be exactly the same, but another update soon.

Revision 1.3 / (download) - annotate - [select for diffs], Thu Mar 12 00:27:07 2015 UTC (5 years, 6 months ago) by mef
Branch: MAIN
CVS Tags: pkgsrc-2015Q1-base, pkgsrc-2015Q1
Changes since 1.2: +4 -4 lines
Diff to previous 1.2 (colored)

Update to 3.0.2
Version 3.0.2: March 11th, 2015
[ Library ]
- On *nix, only export symbols that are part of the API (instead of all
  the internal symbols).

[ X86 ]
- Do not consider 0xF2 as REPNE prefix if it is a part of instruction encoding.
- Fix implicit registers read/written & instruction groups of some instructions.
- More flexible on the order of prefixes, so better handle some tricky
- REPNE prefix can go with STOS & MOVS instructions.
- Fix a compilation bug for X86_REDUCE mode.
- Fix operand size of instructions with operand PTR []

[ Arm ]
- Fix a bug where arm_op_mem.disp is wrongly calculated (in DETAIL mode).
- Fix a bug on handling the If-Then block.

[ Mips ]
- Sanity check for the input size for MIPS64 mode.

[ MSVC ]
- Compile capstone.dll with static runtime MSVCR built in.

[ Python binding ]
- Fix a compiling issue of Cython binding with gcc 4.9.

Revision 1.2 / (download) - annotate - [select for diffs], Sun Feb 22 07:11:48 2015 UTC (5 years, 7 months ago) by mef
Branch: MAIN
Changes since 1.1: +4 -4 lines
Diff to previous 1.1 (colored)

Update to 3.0.1,   Thanks Kamil Rytarowski for information,
Version 3.0.1: February 03, 2015

[ X86 ]

- Properly handle LOCK, REP, REPE & REPNE prefixes.
- Handle undocumented immediates for SSE's (V)CMPPS/PD/SS/SD instructions.
- Print LJUMP/LCALL without * as prefix for Intel syntax.
- Handle REX prefix properly for segment/MMX related instructions (x86_64).
- Instruction with length > 15 is consider invalid.
- Handle some tricky encodings for instructions MOVSXD, FXCH, FCOM, FCOMP,
- Handle some tricky code for some X86_64 instructions with REX prefix.
- Add missing operands in detail mode for PUSH , POP , IN/OUT reg, reg
- MOV32ms & MOV32sm should reference word rather than dword.

[ Arm64 ]

- BL & BLR instructions do not read SP register.
- Print absolute (rather than relative) address for instructions B, BL,

[ Arm ]

- Instructions ADC & SBC do not update flags.
- BL & BLX do not read SP, but PC register.
- Alias LDR instruction with operands [sp], 4 to POP.
- Print immediate operand of MVN instruction in positive hexadecimal form.

[ PowerPC ]

- Fix some compilation bugs when DIET mode is enable.
- Populate SLWI/SRWI instruction details with SH operand.

[ Python binding ]

- Fix a Cython bug when CsInsn.bytes returns a shorten array of bytes.
- Fixed a memory leak for Cython disasm functions when we immaturely quit
  the enumeration of disassembled instructions.
- Fix a NULL memory access issue when SKIPDATA & Detail modes are enable
  at the same time.
- Fix a memory leaking bug when when we stop enumeration over the disassembled
  instructions prematurely.
- Export generic operand types & groups (CS_OP_xxx & CS_GRP_xxx).

Revision 1.1 / (download) - annotate - [select for diffs], Fri Dec 5 11:51:58 2014 UTC (5 years, 9 months ago) by wiz
Branch: MAIN
CVS Tags: pkgsrc-2014Q4-base, pkgsrc-2014Q4

Import capstone-3.0 as devel/capstone, packaged for wip by Kamil

Capstone is a disassembly framework with the target of becoming
the ultimate disasm engine for binary analysis and reversing in
the security community.

Capstone supports multiple hardware architectures, including ARM,
ARM64 (ARMv8), Mips, PPC, Sparc, SystemZ, XCore and X86 (including

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