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Revision 1.14, Sat Oct 8 14:21:12 2016 UTC (7 years, 6 months ago) by kamil
Branch: MAIN
CVS Tags: HEAD
Changes since 1.13: +1 -1
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FILE REMOVED
Remove verilog-current It used to track icarus verilog but there is no update since 20090923. No objections from <gdt>
Revision 1.13 / (download) - annotate - [select for diffs], Fri Aug 11 13:28:08 2006 UTC (17 years, 8 months ago) by dmcmahill
Branch: MAIN
CVS Tags: pkgsrc-2016Q3-base,
pkgsrc-2016Q3,
pkgsrc-2016Q2-base,
pkgsrc-2016Q2,
pkgsrc-2016Q1-base,
pkgsrc-2016Q1,
pkgsrc-2015Q4-base,
pkgsrc-2015Q4,
pkgsrc-2015Q3-base,
pkgsrc-2015Q3,
pkgsrc-2015Q2-base,
pkgsrc-2015Q2,
pkgsrc-2015Q1-base,
pkgsrc-2015Q1,
pkgsrc-2014Q4-base,
pkgsrc-2014Q4,
pkgsrc-2014Q3-base,
pkgsrc-2014Q3,
pkgsrc-2014Q2-base,
pkgsrc-2014Q2,
pkgsrc-2014Q1-base,
pkgsrc-2014Q1,
pkgsrc-2013Q4-base,
pkgsrc-2013Q4,
pkgsrc-2013Q3-base,
pkgsrc-2013Q3,
pkgsrc-2013Q2-base,
pkgsrc-2013Q2,
pkgsrc-2013Q1-base,
pkgsrc-2013Q1,
pkgsrc-2012Q4-base,
pkgsrc-2012Q4,
pkgsrc-2012Q3-base,
pkgsrc-2012Q3,
pkgsrc-2012Q2-base,
pkgsrc-2012Q2,
pkgsrc-2012Q1-base,
pkgsrc-2012Q1,
pkgsrc-2011Q4-base,
pkgsrc-2011Q4,
pkgsrc-2011Q3-base,
pkgsrc-2011Q3,
pkgsrc-2011Q2-base,
pkgsrc-2011Q2,
pkgsrc-2011Q1-base,
pkgsrc-2011Q1,
pkgsrc-2010Q4-base,
pkgsrc-2010Q4,
pkgsrc-2010Q3-base,
pkgsrc-2010Q3,
pkgsrc-2010Q2-base,
pkgsrc-2010Q2,
pkgsrc-2010Q1-base,
pkgsrc-2010Q1,
pkgsrc-2009Q4-base,
pkgsrc-2009Q4,
pkgsrc-2009Q3-base,
pkgsrc-2009Q3,
pkgsrc-2009Q2-base,
pkgsrc-2009Q2,
pkgsrc-2009Q1-base,
pkgsrc-2009Q1,
pkgsrc-2008Q4-base,
pkgsrc-2008Q4,
pkgsrc-2008Q3-base,
pkgsrc-2008Q3,
pkgsrc-2008Q2-base,
pkgsrc-2008Q2,
pkgsrc-2008Q1-base,
pkgsrc-2008Q1,
pkgsrc-2007Q4-base,
pkgsrc-2007Q4,
pkgsrc-2007Q3-base,
pkgsrc-2007Q3,
pkgsrc-2007Q2-base,
pkgsrc-2007Q2,
pkgsrc-2007Q1-base,
pkgsrc-2007Q1,
pkgsrc-2006Q4-base,
pkgsrc-2006Q4,
pkgsrc-2006Q3-base,
pkgsrc-2006Q3,
cwrapper,
cube-native-xorg-base,
cube-native-xorg
Changes since 1.12: +4 -6
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Diff to previous 1.12 (colored)
Update to 20060809 snapshot. There have been several changes since the last packaged snapshot. Those are: -------------------------------------------------- Release Notes for Icarus Verilog Snapshot 20060215 -------------------------------------------------- * Part select of memory words should now work according to Verilog-2001. This also led to some cleanup of the handling of types internally, as well as some infrastructure for general arrays. * Minor fix to parsing of (* *) attributes. * Fix rounding of reals to integers. * Clean up some of the vvp engine related to memories. Remove some dead instructions. -------------------------------------------------- Release Notes for Icarus Verilog Snapshot 20060409 -------------------------------------------------- the most substantial difference in this snapshot the first signs of generate support. The compiler now supports generate loops and has been tested with examples that include wires and gates within the generate scheme. The regression test suite has very few generate tests, so any concise self-testing test programs that use generate would be helpful. Also, instance arrays that use overridden parameters now work properly. Task arguments are a bit more flexible in order to support vendor (notably Xilinx) models that use more interesting task arguments. Runtime support for bi-directional ports had some bugs fixed, along with some other minor run-time bugs. Also, the runtime gains support for typed parameters. And also, there are some new runtime callbacks for events and memories. Parameters had a few types related bugs fixed. They are a bit more flexible now. And various minor compilation errors have been fixed. This includes C/C++ compilation errors fixes, and some configure/Makefile tweaks. -------------------------------------------------- Release Notes for Icarus Verilog Snapshot 20060618 -------------------------------------------------- Add support for system functions in continuous assignments. Allow concatenations as arguments to inout ports. This comes with a small variety of internal part select and concatenation bug fixes. Fix some bugs in constant propagation through ternary expressions. Fix broken subtraction if small constants in certain cases. Fix a few datatype mismatch errors. Make $readmem give warning when input is inadequate for requested range. Fix runtime of nand in continuous assignments. Fix synchronous user defined primiteves to only follow edges. Fix a runtime error in some thread delays processing. Improve limited genvar expression handling. Start a rework of expression elaboration. Make elaboration aware of the expression context width when appropriate in order to better handle expression width and padding. Fix the make rules for parse.cc to reflect that they come from the same source. Fix the autoconf.sh to configure the stub target. Fix portability of the lexor source files on Windows systems. Get rid of the isatty references. Make a stub lround when the system version is missing. -------------------------------------------------- * Release Notes for Snapshot 20060809 -------------------------------------------------- Some handling of real values is improved. Real valued literals are handled in net contexts (continuous assignment, etc.). Also, modulus of real operands now works. (This is an extension to the Verilog standard.) The power operator (**) now works. Signed right shift works properly now. The $sscanf and $fscanf are introduced, and work at least for basic numeric values. The release function now works to undo general force statements, and not just contant force statements. Delay constants up to 64 bits are supported. This at first doesn't seem like an issue, but when precisions are mixed, it becomes surprisingly easy to overflow 32bit delays. The driver is reworked to pass many preprocessor details through a temporary file instead of on the command line of a system(3) call. This prevents confusing and incorrect shell processing of complex strings passed as values to -D flags. Various other little fixes.
Revision 1.12 / (download) - annotate - [select for diffs], Mon Jul 14 09:51:49 2003 UTC (20 years, 9 months ago) by drochner
Branch: MAIN
CVS Tags: pkgsrc-2006Q2-base,
pkgsrc-2006Q2,
pkgsrc-2006Q1-base,
pkgsrc-2006Q1,
pkgsrc-2005Q4-base,
pkgsrc-2005Q4,
pkgsrc-2005Q3-base,
pkgsrc-2005Q3,
pkgsrc-2005Q2-base,
pkgsrc-2005Q2,
pkgsrc-2005Q1-base,
pkgsrc-2005Q1,
pkgsrc-2004Q4-base,
pkgsrc-2004Q4,
pkgsrc-2004Q3-base,
pkgsrc-2004Q3,
pkgsrc-2004Q2-base,
pkgsrc-2004Q2,
pkgsrc-2004Q1-base,
pkgsrc-2004Q1,
pkgsrc-2003Q4-base,
pkgsrc-2003Q4
Changes since 1.11: +4 -7
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Diff to previous 1.11 (colored)
update to snapshot "20030705". There was a couple of snapshots since february; besides bugfixes the major highligths might be: -handling of real values at various places -support for library modules (esp cadence PLI1) -better FPGA support (esp Virtex II) -"vvp" interactive mode added Also converted to buildlink2, and dependencies to libz, libbz2 and readline added.
Revision 1.11 / (download) - annotate - [select for diffs], Tue Feb 4 00:46:08 2003 UTC (21 years, 2 months ago) by dmcmahill
Branch: MAIN
CVS Tags: netbsd-1-6-1-base,
netbsd-1-6-1
Changes since 1.10: +3 -13
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Diff to previous 1.10 (colored)
update to verilog-current-20030202. This is the first packaged (in pkgsrc) snapshot after the verilog-0.7 release. This snapshot adds preliminary support for real variables to the language to the features already found in verilog-0.7.
Revision 1.10 / (download) - annotate - [select for diffs], Tue May 7 00:11:21 2002 UTC (21 years, 11 months ago) by dmcmahill
Branch: MAIN
CVS Tags: pkgviews-base,
pkgviews,
netbsd-1-6-RELEASE-base,
netbsd-1-6,
buildlink2-base,
buildlink2
Changes since 1.9: +17 -4
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Diff to previous 1.9 (colored)
update to verilog-current-20020505 many improvements and bug fixes since the last packaged snapshot including: -added the $sizeof system function as a builtin -In VPI, the simulator event callbacks now work -Concatenation expressions in parameters were broken are broken -added the vpiModule iterator to VPI scope handles
Revision 1.9 / (download) - annotate - [select for diffs], Mon May 21 22:25:19 2001 UTC (22 years, 11 months ago) by dmcmahill
Branch: MAIN
CVS Tags: netbsd-1-5-PATCH003
Changes since 1.8: +13 -6
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Diff to previous 1.8 (colored)
update to verilog-current-20010520. many changes since the last snapshot. Mostly they involve expanded VVP support. The VVP target now passes >200 of the tests from the test suite. While not as complete as the VVM target, VVP is getting closer and its _much_ _much_ faster.
Revision 1.8 / (download) - annotate - [select for diffs], Tue Dec 19 18:53:52 2000 UTC (23 years, 4 months ago) by dmcmahill
Branch: MAIN
CVS Tags: netbsd-1-5-PATCH001
Changes since 1.7: +5 -5
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Diff to previous 1.7 (colored)
update verilog-current to 20001216. Changes since the last packaged snapshot are (from the authors announcements): Icarus Verilog snapshot 20001216 -------------------------------- This is the last snapshot before the holidays, so I hope it has your favorite present in it. A lot of PR#s have been dealt with, and for a brief moment I felt like I was getting ahead of the pending list:-) I've added support for non-integer times, at least in a few contexts. The `timescale directives should interact properly with the decimal point in delays, causing more accurate timing simulations. This should make vendor-supplied libraries work much better. I've added support for signed reg variables. Signed expressions should now generally do the right thing, but this feature needs much more testing, and many more tests in the test suite. However, I do know that signed comparisons should work properly. Bug reports for problems with signed arithmetic are encouraged. Many people have been having troubles with Cygwin compilation. The problem was with the latest version of binutils. Venkat came up with a solution that works with old and new binutils, so you can now compile with the very latest cygwin software. This should make things a lot easier for a lot of people. I've made initial steps toward an HP/UX port. The configure script should detect the right dl library to use, and the t-dll target should be able to load loadable targets. I am looking for a volunteer to take responsibility for the HP/UX port as I have no suitable machines. Said person should be able to compile Icarus Verilog, manage HP/UX specific portability issues, and be able to make precompiled packages when the stable release is out. I'm still looking for a similar volunteer for FreeBSD/{alpha,i386}. Some more progress was made on support for PALs. I'm close to choosing macrocell modes and configuring fuses. Won't be long now, folks. Icarus Verilog snapshot 20001129 -------------------------------- few more constant propagation improvements this time, most notably XOR an XNOR are now fairly complete. These are interesting as they are generated by comparison operators so show up pretty often. And it is common to compare numbers to constants. Thus, there are lots of oppor- tunities for gate elimination! Synthesis of unary ! now works. Unary ~| (reduction nor) should also be in good shape now, as should binary || (logical or). Synthesis of binary && is still a little shaky. Go ahead and file reports if you trip on it. Binary != was broken with XNF synthesis, so that is also fixed, along with a few cases of mangled XNF output. And there were also a few bugs related to the CE of inferred DFFs, that didn't get connected. A *big* problem with synthesis occurred with non-blocking assignment. Icarus Verilog simply failed to synthesize the r-value of the assignment and all kinds of bad things happened. I fixed this, it's better now. Whew! Lots of XNF synthesis bugs fixed! This is what happens when users take the time to submit good bug reports. There are also some bugs related to dead signal elimination that causes Icarus Verilog to crash in some synthesis cases. These have been fixed up so far as I know. I have slightly improved root module detection of iverilog. If there is only one module in a source file, it is pretty obvious that it is the root module, even if it has ports. This is a common case for XNF synthesis (especially when making small macros with Icarus Verilog) and should save some typing and confusion.
Revision 1.7 / (download) - annotate - [select for diffs], Fri Oct 27 03:59:48 2000 UTC (23 years, 5 months ago) by dmcmahill
Branch: MAIN
Changes since 1.6: +3 -2
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Diff to previous 1.6 (colored)
update to 20001021 snapshot of verilog-current from the authors announcement: ----------------------------- The loadable target module API is starting to take shape. That is the major thrust nowadays with Icarus Verilog, after all, so progress is being made here. The biggest change is in fact a philosophy change. The target module now needs only a single symbol -- target_design -- to receive the whole design. The target module can from there and using the API access the entire design randomly. So if you wanted to implement a graphical browser, you could:-) I've added support for the l-values of procedural assignments, and also back pointers to objects that reference ivl_nexus_t objects. This closes the loop so that there should be no dead-ends in the design. I've clarified and expanded the descriptions in the ivl_target.h header file. There should be just about enough documentation to properly used all the various types. (Have any of you tried to write GIMP plug-ins? Have you looked at the libgimp header files? Have you seen any comments there?-( I won't ever sink to that level, I hope.) I've also imtegrated updates to the Cygwin32 port to support loadable targets under Cygwin32. After much struggling, Venkat managed to discover the secret magic needed to get load time symbol binding to work. Hopefully I didn't break it too bad when I changed the API again. (I think it is still fine.)
Revision 1.6 / (download) - annotate - [select for diffs], Sun Aug 6 15:43:35 2000 UTC (23 years, 8 months ago) by dmcmahill
Branch: MAIN
CVS Tags: netbsd-1-5-RELEASE,
netbsd-1-4-PATCH003
Changes since 1.5: +6 -6
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Diff to previous 1.5 (colored)
update to verilog-current-20000805. Changes since the last packaged snapshot are (from the authors announcements): -------------------------------- Icarus Verilog snapshot 20000721 -------------------------------- (first snapshot after the 0.3 release) This snapshot adds no new features or language support, but is working towards more precise interpretation of scheduling and value propagation details. The first thing I've done is redesign the internal Link structure that is used to connect the internal netlist together. There are some aspects of the nexos of a set of links that were carried by the Link class or by external functions. These have been moved to the new Nexus class and linking and structure has improved because of it. This has led me to modify the handing of signal initial values. In practice, the time-0 value of a net is a property of the nexus instead of the objects that are connected together, so I have implemented it so, and in the process fixed a bunch of initial value problems. One new feature that is added is support for non-constant delay expressions. Now, you can even have something like ``#($random%256) <statement>'' and expect it to do what you think. (So now the telephone example in James Lee's "Verilog Qickstart" actually works!) I've added some missing support for various operators in constant expressions. I've also added some more of the friends of $random for those folks who do stochastic modeling. Constant propagation carries some new bug fixes, and some new smarts. It is for example able to detect a mux with a constant 'bz input and replace it with bufif devices, and other clevernesses with logic reduction. -------------------------------- Icarus Verilog snapshot 20000729 -------------------------------- Like I said, the `timescale compiler directive now more or less works. You can now specify timescale for modules, and the compiler will figure out a global design resolution and scale your time values to match. The VCD dumps should reflect the chosen resolution automatically. Floating point notation is not yet supported, we'll see if that turns out to be a problem. A problem with `timescale support is that the compiler will allow unitless modules. This can happen if you have `timescale late in the source file. The default unit is the not-very-intuitive 1s. Frankly, I don't like the `timescale semantics for this sort of reason, but its an accepted standard, so I'm stuck with it. I've also added support for min:typ:max expressions. The compiler chooses one of the three expressions at compile time, based on a compile time switch. You can ask for min typ or max values via the "-Tmin" etc. switch to the iverilog command. If you do not specify a switch, the compiler will choose the typ values but print warnings. The -Ttyp switch will suppress the warnings. I have fixed yet more net initialization bugs. These are getting pretty subtle, now, so you should have a hard time tickling any remaining errors here. I've also fixed a nasty and subtle bug in event expression support. This bug only happened when the design had many event expressions with many conjunctions. Although they are not ready for use, I have made some forward progress with disable statements. I now at least elaborate them, so now I just need to figure out how to make the run-time work out. That's the hard part, I'm afraid. -------------------------------- Icarus Verilog snapshot 20000805 -------------------------------- I've finally dealt with a problem that's been nagging at me for a while. Until now, it has been possible that excessively clever hierarchical references into and out of task scopes could confound symbol lookup. I think I finally put that to rest, and in the process reorganized the netlist format for holding task definitions. It should no longer be possible to confuse name binding in Icarus Verilog. Found and fixed a silly bug in elaborating e?a:'bz and e?'bz:a expressions into bufifN devices. I got the sense of the enable wrong in one of the cases. All fixed (and the test suite updated to catch this silly mistake:-) tri0 and tri1 nets should now work properly. These are mostly a run- time issue which I solved using resolution functions. This is actually a technique that I borrowed from VHDL. For those of you doing XNF synthesis, I fixed up my FF/RAM detector to allow <= assignments in always blocks. This is in fact the preferred way to describe DFFs as <= more accurately simulates their RTL nature. Also found and fixed a few DOS \r\n line end issues in the lexical ana- lyser and the preprocessor. We sometimes forget how tricky these line- end problems can be, and compiler directives are the most susceptible. This problem most likely occurs when you transport files from a DOS environment. (The MAC folks haven't complained much, so either I got it right for them, or Kato took care of the problems for me:-)
Revision 1.5 / (download) - annotate - [select for diffs], Thu May 11 01:33:51 2000 UTC (23 years, 11 months ago) by dmcmahill
Branch: MAIN
Changes since 1.4: +1 -8
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Diff to previous 1.4 (colored)
update to 20000506 snapshot. changes from the last packaged snapshot (from the authors announcement): ---------------Icarus Verilog 20000506 Snapshot------------------ A lot of internal reworking has been done on this, so there might be problems with things like symbol binding. But I think this is much better then the last snapshot. I am once again starting to think about a stable release. I'll shoot for the end of May, so if there is anything you want to see in that release, start pestering me. The big job has been a rewrite of the symbol table that holds signals. The previous elaboration and lookup code for signals/memories did not work properly when hierarchical names were used in the context of tasks and functions. Also, the old table kept all the signals is a single lookup table that failed to take advantage of knowledge of the current scope. All that is changed. signals are now elaborated after parameters and before processes, so all hierarchical accesses should work properly now, no matter how contorted. I've also fixed some bugs with function/task parameter passing. I've also added some infrastructure for supporting system functions, and I've added an implementation of the $random system function. This currently uses the native random(3) C library function, but once I get access to the standardized algorithm, I'll implement that. There are also a few fixes to elaboration of ternary operators. They were a bit touchy about result bit widths. A few preprocessor bugs have been fixed, especially related to the `ifdef/`endif tokens. People are all the sudden starting to use the Icarus Verilog preprocessor, so some long-standing bugs have been caught. The iverilog command had a few path problems fixed, and the remaining necessary switches have been added. I really encourage people to start using iverilog in place of verilog. The test suite now uses iverilog to run the compiler, so should you. There is a man page.
Revision 1.4 / (download) - annotate - [select for diffs], Sun Apr 30 18:15:18 2000 UTC (23 years, 11 months ago) by dmcmahill
Branch: MAIN
Changes since 1.3: +10 -3
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Diff to previous 1.3 (colored)
Update to verilog-current to the 20000428 snapshot. The many bug fixes and changes since the last packaged snapshot are (from the authors announcements): Icarus Verilog 20000428 Snapshot -------------------------------- This one clears up some pretty nasty and subtle bugs. If you've been sending me bug reports, you're probably turning blue holding your breath in anticipation of this snapshot. Breath in, Breath out. Hooray, both force and release work properly. I'm happy about that, release worked out a bit easier then I expected. These should be useful to test bench designers. The big news this past week, however, has been bug fixes. Lots of bug fixes. I got lots of bug reports and I killed pretty nearly all of them. There were lots of nasty icky problems with passing parameters to/from tasks, especially when memory words were involved. I fixed up a whole bunch of these, and now parameter passing should work pretty will, modulus the few remaining bugs I'm not seeing yet. The iverilog command is in better shape now, and I encourage people to use it in place of the older "verilog" driver script. There is a man page for iverilog, and it supports all the switches needed to do simulation and synthesis. I would like people to start getting this driver well tested and the bugs worked out, because it is going to be the main driver come the next stable release. Some neat new XNF features are happening. I synthesize identity compare in XNF, and a few other missing operators. But the really neato part is that I've taught Icarus Verilog to generate PIN records for module ports, so that you can make XNF macros out of Verilog source. If you elaborate a module that has ports, the XNF code generator will automatically generate the necessary symbols so that external XNF tools can link the generated output into larger designs. I've compared the XNF files from Icarus Verilog with those generated by Abel, and they appear the same to my eyes. Icarus Verilog 20000421 Snapshot -------------------------------- Bunches of bug fixes, and a few new features come with this snapshot. This snapshot makes headway in both simulation and synthesis. I'm also starting to make a big dent in my todo list for the 0.3 release. The bunches of little bug fixes in this snapshot are a direct result of bunches of bug reports this past week that I was able to deal with. If you've been reporting bugs, this may contain your fix. I redesigned the process implementation in the vvm backend, so the generated code is a bit cleaner, and threads are lighter weight. And while I was at it, fork/join now should work properly. I know there were a bunch of you out there asking for this, so here it is. I've incorporated into this release improved runtime support for integer multiplication, it should now work now matter how incredibly enormous you make the operands. Thanks to Chris Lattner for contributing the generic multiply. I've improved synthesis somewhat, there were some expressions in some contexts that were not getting synthesized by the -Fsynth functor. This is fixed, and I'm also starting to add some XNF specific optimizations into the -Fxnfio functor. I do sensible things with identity compare, for example. I've added the program ``iverilog'' to be a new driver program written in C instead of as a shell script. This driver supports the -tnull, -txnf and -tvvm targets, as well as the -E flag that causes only the preprocessor to be run. This should be interesting to those of you who are looking for a working preprocessor. I'm still working on the -D and the -I flags, but I expect this program to replace the verilog.sh script before the 0.3 release. Icarus Verilog 20000414 Snapshot -------------------------------- All event handling is now complete. Yet another subject is behind me, and on I go. By complete, I mean that named events, edge triggers, wait, and lists of events all work. This took a little longer then I expected, so some of the other things I wanted to work on had to wait. As a side effect of event and thread scheduling work, I changed the way that threads are generated in vvm. The result is that threads should be a little faster at run time, and a lot faster at compile time. A *LOT* faster at compile time. (Apparently, Verilog XL is still considerably faster, but hey, I'm working on it.)
Revision 1.3 / (download) - annotate - [select for diffs], Sat Mar 25 21:09:16 2000 UTC (24 years ago) by dmcmahill
Branch: MAIN
Changes since 1.2: +4 -4
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Diff to previous 1.2 (colored)
Update to verilog-current-20000318. Notable changes since the last pkg are (from the snapshot announcement): Parameters are complete. What this means is that I finally got around to supporting defparam, and while I was at it I rewrote the entire parameter handling and added the parameter support included in 1364-2000. I have rewritten major portions of the VVM backend. The vvm_nexus class has been introduced to the fray, and all the device implementations in the VVM library now use the nexus to drive and receive values. An advantage of this scheme is that the t-vvm backend code (in ivl proper) is simpler, and so is the generated C++ code. I also removed most of the template classes. This proved to be a huge compile-time benefit (though compiling twice as fast really only matters for large programs) and it doesn't seem likely to hurt run-time performance. A few remain, either because they seemed harmless (the N-wide logic gates) or I couldn't yet figure out a good way to replace them (vvm_bitset_t). A side benefit of this is that the vvm library may now be a modeling library that ordinary humans can use to write their models in C++. This may provide the unexpected benefit of heading me towards incremental compilation of designs. So who was it who was beating me over the head asking for that?-) I also fixed a few minor problems with the preprocessor. Those of you who reported problems with `includes and `defines should check this out.
Revision 1.2 / (download) - annotate - [select for diffs], Tue Mar 7 20:36:53 2000 UTC (24 years, 1 month ago) by dmcmahill
Branch: MAIN
Changes since 1.1: +5 -4
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Diff to previous 1.1 (colored)
fix a patchfile bug which caused parse.cc to be compiled twice.
Revision 1.1 / (download) - annotate - [select for diffs], Tue Mar 7 16:09:16 2000 UTC (24 years, 1 month ago) by dmcmahill
Branch: MAIN
Initial revision