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Revision 1.31 / (download) - annotate - [select for diffs], Sat Nov 26 17:10:24 2011 UTC (5 months, 3 weeks ago) by joerg
Branch: MAIN
CVS Tags: pkgsrc-2012Q1-base,
pkgsrc-2012Q1,
pkgsrc-2011Q4-base,
pkgsrc-2011Q4,
HEAD
Changes since 1.30: +2 -1
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Fix C++
Revision 1.30 / (download) - annotate - [select for diffs], Sun Feb 28 15:59:19 2010 UTC (2 years, 2 months ago) by dmcmahill
Branch: MAIN
CVS Tags: pkgsrc-2011Q3-base,
pkgsrc-2011Q3,
pkgsrc-2011Q2-base,
pkgsrc-2011Q2,
pkgsrc-2011Q1-base,
pkgsrc-2011Q1,
pkgsrc-2010Q4-base,
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pkgsrc-2010Q3,
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Changes since 1.29: +4 -4
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Update to the 20090923 snapshot. It has been a long time since the last update to this snapshot package. Besides the various upstream changes, also - add LICENSE - add DESTDIR support (partially enabled by upstream fixes) Release Notes for Snapshot 20090923 This is the first snapshot after the split from the 0.9 release. Mostly, this snapshot is loaded with 7 months worth of bug fixes.
Revision 1.29 / (download) - annotate - [select for diffs], Thu Mar 1 01:03:45 2007 UTC (5 years, 2 months ago) by dmcmahill
Branch: MAIN
CVS Tags: pkgsrc-2009Q4-base,
pkgsrc-2009Q4,
pkgsrc-2009Q3-base,
pkgsrc-2009Q3,
pkgsrc-2009Q2-base,
pkgsrc-2009Q2,
pkgsrc-2009Q1-base,
pkgsrc-2009Q1,
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pkgsrc-2008Q4,
pkgsrc-2008Q3-base,
pkgsrc-2008Q3,
pkgsrc-2008Q2-base,
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pkgsrc-2008Q1,
pkgsrc-2007Q4-base,
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pkgsrc-2007Q2,
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pkgsrc-2007Q1,
cwrapper,
cube-native-xorg-base,
cube-native-xorg
Changes since 1.28: +4 -4
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update to verilog-current-20070227 Release Notes for Icarus Verilog Snapshot 20070227 * Fix some problems with specify block parsing. Detect some cases that are parsed but not properly implemented yet and issue warnings or errors. Also fixed a few problems with inertial delay model timing. * Detect is some cases Verilog source errors that can be better reported to users. This includes more specific error messages for certain syntax errors. * Fix problems with overridden continuous assignments. * Hide bool types from logic type as far as VPI is concerned, for the sake of compatibility. * Fix a variety of code generator expression lifetime bugs that caused obscure (and wrong) output results in behavioral code. * iverilog-vpi uses the compiler selected at build time. * Rework handling of strings to handle escape sequences properly. * Fix some handling of real values in some expression types. * Get padding of sized, unsigned numbers when x or z are involved. * Many, many more misc. bug fixes. * Add an assert mechinism that improves usefulness of bug reports by reporting source file line numbers when available. * Compile fixes, using inttypes.h instead of stdint for portability. * Various spelling fixes.
Revision 1.28 / (download) - annotate - [select for diffs], Wed Feb 21 23:18:44 2007 UTC (5 years, 3 months ago) by dmcmahill
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Update to verilog-current-20070123 Release Note for Icarus Verilog Snapshot 20070123 Handling of arrays has been rewritten to allow support for net arrays. This caused ivl_target API changes, as well as elaboration and vvp run time changes. There may be bits of the old method lingering in the source code. Improve support for constant power (**) expressions, and other constant exppressions that are passed to functions/tasks. Improve elaboration of for-loop increment expressions. There were some bugs there that are not fixed. Fix argument width calculations for shift operations. Constant ector expressions can have real constants. Handle this at run time where needed. Fix some bad lookaside optimizations for assignments to l-value part selects.
Revision 1.27 / (download) - annotate - [select for diffs], Tue Oct 10 00:19:49 2006 UTC (5 years, 7 months ago) by dmcmahill
Branch: MAIN
CVS Tags: pkgsrc-2006Q4-base,
pkgsrc-2006Q4
Changes since 1.26: +4 -4
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update to verilog-current-20061009 * Release Notes for Icarus Verilog Snapshot 20061009 The Big news is support for delay path timing is specify blocks. This includes delay paths and specparams. Back annotation of specify path timings are not yet implemented. The "-g" flag has been made a bit more general so that individual compiler features can be turned on/off. This for example allows for turning off specify block support and Icarus Verilog extensions, as well as select language generation. A variety of bug fixes have been included. - Missing symbols on Windows fixed. - mingw build instructions reworked. - Fix internal handling of -D__ICARUS__ define - Fix crash of driver when -M flag is used. - Fix configure detection of host in some subdirectories. - Handle non-constant delays of index non-blocking assignments. - $scanf support for real values. - Fix scheduling of RWsync vs. ROSync callbacks. - Fix vpi_put_userdata return value. The iverilog-vpi command now allows .cpp files to stand for C++ source.
Revision 1.26 / (download) - annotate - [select for diffs], Fri Aug 11 13:28:08 2006 UTC (5 years, 9 months ago) by dmcmahill
Branch: MAIN
CVS Tags: pkgsrc-2006Q3-base,
pkgsrc-2006Q3
Changes since 1.25: +5 -5
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Update to 20060809 snapshot. There have been several changes since the last packaged snapshot. Those are: -------------------------------------------------- Release Notes for Icarus Verilog Snapshot 20060215 -------------------------------------------------- * Part select of memory words should now work according to Verilog-2001. This also led to some cleanup of the handling of types internally, as well as some infrastructure for general arrays. * Minor fix to parsing of (* *) attributes. * Fix rounding of reals to integers. * Clean up some of the vvp engine related to memories. Remove some dead instructions. -------------------------------------------------- Release Notes for Icarus Verilog Snapshot 20060409 -------------------------------------------------- the most substantial difference in this snapshot the first signs of generate support. The compiler now supports generate loops and has been tested with examples that include wires and gates within the generate scheme. The regression test suite has very few generate tests, so any concise self-testing test programs that use generate would be helpful. Also, instance arrays that use overridden parameters now work properly. Task arguments are a bit more flexible in order to support vendor (notably Xilinx) models that use more interesting task arguments. Runtime support for bi-directional ports had some bugs fixed, along with some other minor run-time bugs. Also, the runtime gains support for typed parameters. And also, there are some new runtime callbacks for events and memories. Parameters had a few types related bugs fixed. They are a bit more flexible now. And various minor compilation errors have been fixed. This includes C/C++ compilation errors fixes, and some configure/Makefile tweaks. -------------------------------------------------- Release Notes for Icarus Verilog Snapshot 20060618 -------------------------------------------------- Add support for system functions in continuous assignments. Allow concatenations as arguments to inout ports. This comes with a small variety of internal part select and concatenation bug fixes. Fix some bugs in constant propagation through ternary expressions. Fix broken subtraction if small constants in certain cases. Fix a few datatype mismatch errors. Make $readmem give warning when input is inadequate for requested range. Fix runtime of nand in continuous assignments. Fix synchronous user defined primiteves to only follow edges. Fix a runtime error in some thread delays processing. Improve limited genvar expression handling. Start a rework of expression elaboration. Make elaboration aware of the expression context width when appropriate in order to better handle expression width and padding. Fix the make rules for parse.cc to reflect that they come from the same source. Fix the autoconf.sh to configure the stub target. Fix portability of the lexor source files on Windows systems. Get rid of the isatty references. Make a stub lround when the system version is missing. -------------------------------------------------- * Release Notes for Snapshot 20060809 -------------------------------------------------- Some handling of real values is improved. Real valued literals are handled in net contexts (continuous assignment, etc.). Also, modulus of real operands now works. (This is an extension to the Verilog standard.) The power operator (**) now works. Signed right shift works properly now. The $sscanf and $fscanf are introduced, and work at least for basic numeric values. The release function now works to undo general force statements, and not just contant force statements. Delay constants up to 64 bits are supported. This at first doesn't seem like an issue, but when precisions are mixed, it becomes surprisingly easy to overflow 32bit delays. The driver is reworked to pass many preprocessor details through a temporary file instead of on the command line of a system(3) call. This prevents confusing and incorrect shell processing of complex strings passed as values to -D flags. Various other little fixes.
Revision 1.25 / (download) - annotate - [select for diffs], Wed Jan 25 12:11:01 2006 UTC (6 years, 3 months ago) by dmcmahill
Branch: MAIN
CVS Tags: pkgsrc-2006Q2-base,
pkgsrc-2006Q2,
pkgsrc-2006Q1-base,
pkgsrc-2006Q1
Changes since 1.24: +4 -4
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update to 20060124 snapshot. A few new features have been added to allow proper simulation with newer Xilinx UNISIM models. (They are starting to use Verilog 2001 features.) And also various bug fixes in this release. -- Primitive and continuous assign delays can now be non-constant. This needed some new run-time support, so vvp had a slight format change, and certain new optimizations follow as a result. -- Bug handling certain constant sub-expressions in concatenation expressions. Also, allow concat expressions in constant contexts. -- Support for wide divide expressions. -- Fixes for stubborn compilers. -- Fix bugs in padding of signed expressions. -- More fixes for following the data types of expressions.
Revision 1.24 / (download) - annotate - [select for diffs], Wed Feb 23 14:59:25 2005 UTC (7 years, 2 months ago) by agc
Branch: MAIN
CVS Tags: pkgsrc-2005Q4-base,
pkgsrc-2005Q4,
pkgsrc-2005Q3-base,
pkgsrc-2005Q3,
pkgsrc-2005Q2-base,
pkgsrc-2005Q2,
pkgsrc-2005Q1-base,
pkgsrc-2005Q1
Changes since 1.23: +2 -1
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Diff to previous 1.23 (colored)
Add RMD160 digests in addition to SHA1 ones.
Revision 1.23 / (download) - annotate - [select for diffs], Sat Nov 27 02:50:09 2004 UTC (7 years, 5 months ago) by dmcmahill
Branch: MAIN
CVS Tags: pkgsrc-2004Q4-base,
pkgsrc-2004Q4
Changes since 1.22: +3 -3
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Diff to previous 1.22 (colored)
update to verilog-current 20041004. Release Notes for Icarus Verilog Snapshot 20041004 Some minor Makefile bugs have been fixed, and source file text formatting has in some cases been normalized for release. Also, configure scripts have been factored for a more consistent build. Fixed continuous assignments to carry strength when needed for correct behavior. This bug led to subtly incorrect reset behavior, but could have caused strength modeling errors in a variety of situations. Fixed some <= vs >= behaviors to be consistent. The results of these comparisons, when sized values are involved, are more standard now.
Revision 1.22 / (download) - annotate - [select for diffs], Tue Sep 21 02:23:19 2004 UTC (7 years, 8 months ago) by dmcmahill
Branch: MAIN
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update to verilog-current-20040915. Changes in this snapshot: The big news is that module instance arrays now work. Gate and UDP instance arrays have worked for a while, but module instance arrays were more tricky because of the scope arrys they create. The issues have been dealt with, and module instance arrays are now supported. An interesting but subtle set of bugs in the evaluation of ternary expressions has been fixed. The problems expressed themselves when the condition expression was constant. Degenerate wait statements now work properly. The @* syntax apparently missed sensitivities in l-value expressions of assignment statements. This led to subtle bugs in carefully crafted bits of code. Verilog attributes are properly parsed in a few more contexts. Also, some specify syntax cases have been fixed. Some minor spelling and documentation errors have been fixed, along with assorted compiler warnings.
Revision 1.21 / (download) - annotate - [select for diffs], Thu Sep 2 01:55:47 2004 UTC (7 years, 8 months ago) by dmcmahill
Branch: MAIN
CVS Tags: pkgsrc-2004Q3-base,
pkgsrc-2004Q3
Changes since 1.20: +3 -3
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Diff to previous 1.20 (colored)
update to verilog-current-20040828 changes include: Added support for the `default_nettype directine, including the default net type of "none", which turns off implicit net declarations. Signed /, % and >>> in nets should now work properly. Also, various operators of all sorts applied to constants have been improved. Ranges now work on localparams. Added the system tasks $unsigned, $is_signed, $mti_random and $mti-dist_uniform. See the make README.txt for a description of these system functions. Also, flesh out the standard random number generators to match the sequences generated by other compilers. There is now an "sft" file that describes to the compiler the return value of system functions. This allows user supplied system functions to have interesting return types. See "SYSTEM FUNCTIO TABLE FILES" in the iverilog man page. Include a sft file for the system functions, and move the system functions over to that mechinism. Fix the behavior of $fgets in tight fitting result buffers. A variety of compilation environment fixes have been added. These involve configure scripts and Makefiles. And of course a variety of other bug fixes, and so on and so forth.
Revision 1.20 / (download) - annotate - [select for diffs], Mon Jun 7 01:09:50 2004 UTC (7 years, 11 months ago) by dmcmahill
Branch: MAIN
CVS Tags: pkgsrc-2004Q2-base,
pkgsrc-2004Q2
Changes since 1.19: +3 -3
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update to verilog-current-20040606
* Release Notes for Icarus Verilog Snapshot 20040606
Ports of primitives can bind by name as well as by position. Also
support Verilog 2001 style port declarations for primitives.
System function return types can now be specified by system function
table files. System Function Table Files are described in the iverilog
man page. Also include better system function return types in VPI.
Non-blocking assign of real values to real variables now works.
Properly handle nul strings ("") as 8bit values. This is a weirdness
legacy of XL.
Fix some synthesis problems for logical OR and logical AND. Bitwise OR
and AND were fine. These fixes affected simulation as well.
Handle wait statements with all sorts of constant values. These are
sometimes weird, bug legal.
Handle Negative value reals, and a few other bugs related to real
numbers.
Change internal use of identifiers to perm_strings for better
performance.
Functions returning unsupported types now generate error
messages. Previously, they would quietly generate bad
code. Infrastructure is also added to eventually support arbitrary
function return types.
Better compile-time support for Cygwin vs mingw32.
The ipal target is removed from this source. (ipal is now an add-on
package that is compiled seperately.)
Revision 1.19 / (download) - annotate - [select for diffs], Tue Mar 2 15:34:07 2004 UTC (8 years, 2 months ago) by drochner
Branch: MAIN
CVS Tags: pkgsrc-2004Q1-base,
pkgsrc-2004Q1
Changes since 1.18: +3 -3
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update to the 20040220 snapshot changes: bugfixes, VPI extensions
Revision 1.18 / (download) - annotate - [select for diffs], Mon Aug 25 11:21:50 2003 UTC (8 years, 9 months ago) by drochner
Branch: MAIN
CVS Tags: pkgsrc-2003Q4-base,
pkgsrc-2003Q4
Changes since 1.17: +3 -3
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Diff to previous 1.17 (colored)
update to the 20030815 shapshot changes are basically bugfixes, and improvements in the FPGA synthesis area
Revision 1.17 / (download) - annotate - [select for diffs], Mon Jul 14 09:51:48 2003 UTC (8 years, 10 months ago) by drochner
Branch: MAIN
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update to snapshot "20030705". There was a couple of snapshots since february; besides bugfixes the major highligths might be: -handling of real values at various places -support for library modules (esp cadence PLI1) -better FPGA support (esp Virtex II) -"vvp" interactive mode added Also converted to buildlink2, and dependencies to libz, libbz2 and readline added.
Revision 1.16 / (download) - annotate - [select for diffs], Tue Feb 4 00:46:07 2003 UTC (9 years, 3 months ago) by dmcmahill
Branch: MAIN
CVS Tags: netbsd-1-6-1-base,
netbsd-1-6-1
Changes since 1.15: +4 -4
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update to verilog-current-20030202. This is the first packaged (in pkgsrc) snapshot after the verilog-0.7 release. This snapshot adds preliminary support for real variables to the language to the features already found in verilog-0.7.
Revision 1.15 / (download) - annotate - [select for diffs], Tue Oct 22 02:52:18 2002 UTC (9 years, 7 months ago) by dmcmahill
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update to verilog-current-20021019 Release Notes for Icarus Verilog Snapshot 20021019 The synthesizer now detects asynchronous set/reset inputs to DFF devices. The fpga and vvp code generators have been updated to support these signals. The vvp code generator also gained some register management code that improves the thread register usage. This redoces code size for certain common cases, and thus improves simulation performance. The requirements on `ifdef and related compiler directives has been relaxed, to correspond to more common behavior. The parameter range support crashed if the range expressions had parameters in them. This is fixed, and some signed-ness bugs fixed along with it. Rearrange some of the configure script tests to assure better compatibility accross platforms.
Revision 1.14 / (download) - annotate - [select for diffs], Thu Oct 17 01:38:43 2002 UTC (9 years, 7 months ago) by dmcmahill
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Changes since 1.13: +2 -1
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fix the iverilog-vpi shell script (bash-isms)
Revision 1.13 / (download) - annotate - [select for diffs], Sun Oct 13 23:01:27 2002 UTC (9 years, 7 months ago) by dmcmahill
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Changes since 1.12: +3 -3
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update to verilog-current-20020921 snapshot. Many improvemnts in the synthesis code and bug fixes in the simulation code since the last packaged snapshot.
Revision 1.12 / (download) - annotate - [select for diffs], Thu Aug 29 11:15:57 2002 UTC (9 years, 8 months ago) by dmcmahill
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update to verilog-current-20020828 Release Notes for Snapshot 20020828 This snapshot adds support for parameter and localparam bit ranges. This is a IEEE1364-2001 feature, although some -1995 compilers have supported it in the past. Fixed a *nasty* and slippery bug with the evaluation of bit select of nets. (Bit select of variables was unaffected.) The symptoms did not clearly point to the problem, so bugs related to it were often mis- reported. Gate delays were lost when constants were propagated to their inputs. This is fixed for the known broken cases. Also, mux output delays have been fixed. Also, release statements that apply to elided nets are turned into no-ops. The r-values of non-blocking assignments are now precalculated at compile time, if possible, as is done with blocking assignments. This speeds up constant propagation, and is more thorough. Also optimize subtraction of small constants from vectors, with the new %subi instruction in vvp. This saves some in code size and thread footprint. Handling of x in r-value bit selects and memory word selects did the wrong thing. Now they do the right thing. Also, x in the selector of ?: ternary operators does the right (and complicated) thing now. In the process, a fork-join code generator bug was fixed. Several bugs with time formatting have been fixed. Temporaries in sequential blocks are detected by the synthesizer, and converted into wires when needed. This expands support for combinational logic synthesis.
Revision 1.11 / (download) - annotate - [select for diffs], Sat Aug 24 04:36:45 2002 UTC (9 years, 9 months ago) by dmcmahill
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Changes since 1.10: +3 -3
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update to verilog-current-20020817. Many many changes and bug fixes since the last packaged snapshot. Better language coverage, better performance, improved synthesis, fixed bugs. Too much to list here.
Revision 1.10 / (download) - annotate - [select for diffs], Tue May 7 00:11:20 2002 UTC (10 years ago) by dmcmahill
Branch: MAIN
CVS Tags: pkgviews-base,
pkgviews,
netbsd-1-6-RELEASE-base,
netbsd-1-6,
buildlink2-base,
buildlink2
Changes since 1.9: +4 -4
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Diff to previous 1.9 (colored)
update to verilog-current-20020505 many improvements and bug fixes since the last packaged snapshot including: -added the $sizeof system function as a builtin -In VPI, the simulator event callbacks now work -Concatenation expressions in parameters were broken are broken -added the vpiModule iterator to VPI scope handles
Revision 1.9 / (download) - annotate - [select for diffs], Thu Mar 28 03:07:29 2002 UTC (10 years, 1 month ago) by dmcmahill
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CVS Tags: netbsd-1-5-PATCH003
Changes since 1.8: +3 -3
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update to verilog-current-20020317 Release Notes for snapshot 20020317 The first difference in this snapshot from the 0.6 release is that vvm is no longer compiled by default. If you want to compile vvm, you must enable it at configure time (--enable-vvm) and rebuild from scratch. Eventually, vvm will disappear from the release altogether. The next major difference is new support for user defined functions. It is new support, so it is bound to be buggy, but it should be somewhat complete. The major problem has been solved, so all that remains are bugs around the edges. The vvp run-time scheduler has been changed slightly. The run time behavior is getting increasingly precise and picky, as larger designs are thrown at the compiler. The change introduced in this snapshot fixes logic gates to not propagate zero-time pulses, and thus fixes some weird bugs in large designs. I've also added initial support for the Verilog 200x pragma comment, which are (* *) pairs. For now, the compiler ignores them as comments. This is what a compiler is supposed to do with anything that is not specifically recognized. Also, Tony (Anthony Bybell) has added LXT dump support. The LXT output file is a waveform output format that is much more compact then VCD. The gtkwave waveform viewer supports the LXT format, and should operate a bit faster when viewing LXT files. For now, there are separate system tasks for managing LXT output ($lxt_dumpvars, etc) but eventually the dump format will be selectable by environment variable or command line switch. This snapshot also includes various random bug fixes and improved error messages for incorrect code.
Revision 1.8 / (download) - annotate - [select for diffs], Wed Jan 16 19:33:18 2002 UTC (10 years, 4 months ago) by dmcmahill
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update to verilog-current-20020112 many many changes since the last packaged snapshot. A brief sampling of the changes (which include many bug fixes and enhancements) is: A variety of little problems with $display format strings have been fixed. The % operand should now simulate properly. Also, the * operator is a little bit more optimized, and works in constant expressions. Several bugs in strength modeling have been fixed. This includes drive strengths on continuous assignments, which in the past generated code without the strengths. Also, vvp gained some missing support for constants with strength. I think that strength modeling is now complete. vpi_get_vlog_info support has been added to the vvp run-time. This is a PLI function that allows access to run-time command flags. Also, vpi access to root modules now works properly.
Revision 1.7 / (download) - annotate - [select for diffs], Sat Dec 15 18:43:37 2001 UTC (10 years, 5 months ago) by dmcmahill
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update to verilog-current-20011209 snapshot. Many changes since the last packaged snapshot. A sampling of these are: Support for hierarchical names has been largely rewritten. The major consequence of this is that escaped names now have much better support. By now, most any combination of escaped and hierarchical name should work properly, for nets, parameters, and anything else. Output delays for primitive gates, including user defined primitivies, should now work properly. Delays on nets still do not work, although the parser now parses them and prints a "sorry" message. Bugs in support for division(/) and modulus (%) have been fixed. Bugs in l-values of synthesized DFF devices have been fixed. These bugs were related to part selects of vectors in l-values. A few XNF code generator bugs and limitations were fixed. And as usual, a variety of miscellaneous bugs have been fixed in this snapshot. The bit size of the results of some unary redunction operators is now properly handled. Also, similar problems with logical functions have been fixed. force/release now works for variables, though not yet for nets. Assign/deassign already work. many other bugfixes
Revision 1.6 / (download) - annotate - [select for diffs], Wed Oct 24 12:27:11 2001 UTC (10 years, 7 months ago) by dmcmahill
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Changes since 1.5: +3 -3
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update to verilog-current-20011020. changes since last snapshot include: - addition of a fpga target for synthesis. outputs edif, optimized for xilinx virtex parts. - fixed bug with synthesis of != - fixed bug in hex constant parsing - fixed vvp bug with subtracting very wide words - much improved VCD output - many other bug fixes and robustness improvements.
Revision 1.5 / (download) - annotate - [select for diffs], Tue Jul 3 18:23:46 2001 UTC (10 years, 10 months ago) by dmcmahill
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Changes since 1.4: +3 -5
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Diff to previous 1.4 (colored)
update to 20010630 snapshot. changes are: ----------- RELEASE NOTE FOR ICARUS VERILOG 20010630 I've done some cleanup of the mingw port of Icarus Verilog. I've also added instructions for how to build Icarus Verilog under mingw. I'm working on making that the preferred way to support Windows, and when I make the 0.5 release I will make Windows binaries this way. Anyhow, feedback on the build instructions and the build results using the instructions in mingw.txt are welcome. I've make "vvp" the default target type. The older vvm behavior is available with the "-tvvm" flag to iverilog, but I would rather be told about (and fix) bugs in the vvp code generator and run time. I've added support for the (unsigned) right shift operator. The left shift has been working for a while now, but right shift somehow slipped through the cracks. The shift operators still don't quite work in structural contexts, but they should show up sometime next week. I've finally got VCD output working properly with vvp. It may even be better then with vvm, although some internal symbols are still generated. A few odd bugs have been fixed, including a code generation error for xnf, and error checking of user defined function parameters.
Revision 1.4 / (download) - annotate - [select for diffs], Mon May 21 22:25:19 2001 UTC (11 years ago) by dmcmahill
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Changes since 1.3: +6 -5
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update to verilog-current-20010520. many changes since the last snapshot. Mostly they involve expanded VVP support. The VVP target now passes >200 of the tests from the test suite. While not as complete as the VVM target, VVP is getting closer and its _much_ _much_ faster.
Revision 1.3 / (download) - annotate - [select for diffs], Sat Apr 28 03:45:05 2001 UTC (11 years ago) by dmcmahill
Branch: MAIN
CVS Tags: netbsd-1-5-PATCH001
Changes since 1.2: +2 -2
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Diff to previous 1.2 (colored)
update missing distinfo file from update. Thanks to Thomas Klausner for catching this one.
Revision 1.2 / (download) - annotate - [select for diffs], Thu Apr 19 16:27:02 2001 UTC (11 years, 1 month ago) by agc
Branch: MAIN
Changes since 1.1: +2 -1
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Move to sha1 digests, and add distfile sizes.
Revision 1.1 / (download) - annotate - [select for diffs], Tue Apr 17 10:30:26 2001 UTC (11 years, 1 month ago) by agc
Branch: MAIN
+ move the distfile digest/checksum value from files/md5 to distinfo + move the patch digest/checksum values from files/patch-sum to distinfo