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CVS log for pkgsrc/cad/verilog-current/Attic/Makefile

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Request diff between arbitrary revisions

Default branch: MAIN
Current tag: MAIN

Revision 1.62, Sat Oct 8 14:21:12 2016 UTC (6 years, 7 months ago) by kamil
Branch: MAIN
Changes since 1.61: +1 -1 lines

Remove verilog-current

It used to track icarus verilog but there is no update since 20090923.

No objections from <gdt>

Revision 1.61 / (download) - annotate - [select for diffs], Thu Oct 9 14:06:01 2014 UTC (8 years, 7 months ago) by wiz
Branch: MAIN
CVS Tags: pkgsrc-2016Q3-base, pkgsrc-2016Q3, pkgsrc-2016Q2-base, pkgsrc-2016Q2, pkgsrc-2016Q1-base, pkgsrc-2016Q1, pkgsrc-2015Q4-base, pkgsrc-2015Q4, pkgsrc-2015Q3-base, pkgsrc-2015Q3, pkgsrc-2015Q2-base, pkgsrc-2015Q2, pkgsrc-2015Q1-base, pkgsrc-2015Q1, pkgsrc-2014Q4-base, pkgsrc-2014Q4
Changes since 1.60: +1 -3 lines
Diff to previous 1.60 (colored)

Remove pkgviews: don't set PKG_INSTALLATION_TYPES in Makefiles.

Revision 1.60 / (download) - annotate - [select for diffs], Fri Nov 29 12:53:45 2013 UTC (9 years, 5 months ago) by joerg
Branch: MAIN
CVS Tags: pkgsrc-2014Q3-base, pkgsrc-2014Q3, pkgsrc-2014Q2-base, pkgsrc-2014Q2, pkgsrc-2014Q1-base, pkgsrc-2014Q1, pkgsrc-2013Q4-base, pkgsrc-2013Q4
Changes since 1.59: +6 -1 lines
Diff to previous 1.59 (colored)

Has race conditions during build.

Revision 1.59 / (download) - annotate - [select for diffs], Mon Jul 15 02:02:18 2013 UTC (9 years, 10 months ago) by ryoon
Branch: MAIN
CVS Tags: pkgsrc-2013Q3-base, pkgsrc-2013Q3
Changes since 1.58: +3 -2 lines
Diff to previous 1.58 (colored)

* .include "../../devel/readline/" with USE_GNU_READLINE=yes
  are replaced with .include "../../devel/readline/", and
  USE_GNU_READLINE are removed,

* .include "../../devel/readline/" without USE_GNU_READLINE
  are replaced with .include "../../mk/".

Revision 1.58 / (download) - annotate - [select for diffs], Mon Oct 8 13:25:17 2012 UTC (10 years, 7 months ago) by asau
Branch: MAIN
CVS Tags: pkgsrc-2013Q2-base, pkgsrc-2013Q2, pkgsrc-2013Q1-base, pkgsrc-2013Q1, pkgsrc-2012Q4-base, pkgsrc-2012Q4
Changes since 1.57: +1 -2 lines
Diff to previous 1.57 (colored)

Drop PKG_DESTDIR_SUPPORT setting, "user-destdir" is default these days.

Revision 1.57 / (download) - annotate - [select for diffs], Sun Feb 28 15:59:18 2010 UTC (13 years, 3 months ago) by dmcmahill
Branch: MAIN
CVS Tags: pkgsrc-2012Q3-base, pkgsrc-2012Q3, pkgsrc-2012Q2-base, pkgsrc-2012Q2, pkgsrc-2012Q1-base, pkgsrc-2012Q1, pkgsrc-2011Q4-base, pkgsrc-2011Q4, pkgsrc-2011Q3-base, pkgsrc-2011Q3, pkgsrc-2011Q2-base, pkgsrc-2011Q2, pkgsrc-2011Q1-base, pkgsrc-2011Q1, pkgsrc-2010Q4-base, pkgsrc-2010Q4, pkgsrc-2010Q3-base, pkgsrc-2010Q3, pkgsrc-2010Q2-base, pkgsrc-2010Q2, pkgsrc-2010Q1-base, pkgsrc-2010Q1
Changes since 1.56: +5 -4 lines
Diff to previous 1.56 (colored)

Update to the 20090923 snapshot.

It has been a long time since the last update to this snapshot package.
Besides the various upstream changes, also

- add DESTDIR support (partially enabled by upstream fixes)

Release Notes for Snapshot 20090923

This is the first snapshot after the split from the 0.9
release. Mostly, this snapshot is loaded with 7 months worth of bug

Revision 1.56 / (download) - annotate - [select for diffs], Wed May 20 00:58:07 2009 UTC (14 years ago) by wiz
Branch: MAIN
CVS Tags: pkgsrc-2009Q4-base, pkgsrc-2009Q4, pkgsrc-2009Q3-base, pkgsrc-2009Q3, pkgsrc-2009Q2-base, pkgsrc-2009Q2
Changes since 1.55: +2 -1 lines
Diff to previous 1.55 (colored)

Recursive ABI depends update and PKGREVISION bump for readline-6.0 shlib
major change.

Reported by Robert Elz in PR 41345.

Revision 1.55 / (download) - annotate - [select for diffs], Thu Mar 1 01:03:45 2007 UTC (16 years, 3 months ago) by dmcmahill
Branch: MAIN
CVS Tags: pkgsrc-2009Q1-base, pkgsrc-2009Q1, pkgsrc-2008Q4-base, pkgsrc-2008Q4, pkgsrc-2008Q3-base, pkgsrc-2008Q3, pkgsrc-2008Q2-base, pkgsrc-2008Q2, pkgsrc-2008Q1-base, pkgsrc-2008Q1, pkgsrc-2007Q4-base, pkgsrc-2007Q4, pkgsrc-2007Q3-base, pkgsrc-2007Q3, pkgsrc-2007Q2-base, pkgsrc-2007Q2, pkgsrc-2007Q1-base, pkgsrc-2007Q1, cwrapper, cube-native-xorg-base, cube-native-xorg
Changes since 1.54: +2 -2 lines
Diff to previous 1.54 (colored)

update to verilog-current-20070227

Release Notes for Icarus Verilog Snapshot 20070227

* Fix some problems with specify block parsing. Detect some cases that
  are parsed but not properly implemented yet and issue warnings or
  errors. Also fixed a few problems with inertial delay model timing.

* Detect is some cases Verilog source errors that can be better
  reported to users. This includes more specific error messages for
  certain syntax errors.

* Fix problems with overridden continuous assignments.

* Hide bool types from logic type as far as VPI is concerned, for the
  sake of compatibility.

* Fix a variety of code generator expression lifetime bugs that caused
  obscure (and wrong) output results in behavioral code.

* iverilog-vpi uses the compiler selected at build time.

* Rework handling of strings to handle escape sequences properly.

* Fix some handling of real values in some expression types.

* Get padding of sized, unsigned numbers when x or z are involved.

* Many, many more misc. bug fixes.

* Add an assert mechinism that improves usefulness of bug reports by
  reporting source file line numbers when available.

* Compile fixes, using inttypes.h instead of stdint for portability.

* Various spelling fixes.

Revision 1.54 / (download) - annotate - [select for diffs], Wed Feb 21 23:18:44 2007 UTC (16 years, 3 months ago) by dmcmahill
Branch: MAIN
Changes since 1.53: +2 -2 lines
Diff to previous 1.53 (colored)

Update to verilog-current-20070123

Release Note for Icarus Verilog Snapshot 20070123

Handling of arrays has been rewritten to allow support for net
arrays. This caused ivl_target API changes, as well as elaboration and
vvp run time changes. There may be bits of the old method lingering in
the source code.

Improve support for constant power (**) expressions, and other
constant exppressions that are passed to functions/tasks.

Improve elaboration of for-loop increment expressions. There were some
bugs there that are not fixed.

Fix argument width calculations for shift operations.

Constant ector expressions can have real constants. Handle this at run
time where needed.

Fix some bad lookaside optimizations for assignments to l-value part

Revision 1.53 / (download) - annotate - [select for diffs], Tue Oct 10 00:19:49 2006 UTC (16 years, 7 months ago) by dmcmahill
Branch: MAIN
CVS Tags: pkgsrc-2006Q4-base, pkgsrc-2006Q4
Changes since 1.52: +2 -2 lines
Diff to previous 1.52 (colored)

update to verilog-current-20061009

* Release Notes for Icarus Verilog Snapshot 20061009

The Big news is support for delay path timing is specify blocks. This
includes delay paths and specparams. Back annotation of specify path
timings are not yet implemented.

The "-g" flag has been made a bit more general so that individual
compiler features can be turned on/off. This for example allows for
turning off specify block support and Icarus Verilog extensions, as
well as select language generation.

A variety of bug fixes have been included.
- Missing symbols on Windows fixed.
- mingw build instructions reworked.
- Fix internal handling of -D__ICARUS__ define
- Fix crash of driver when -M flag is used.
- Fix configure detection of host in some subdirectories.
- Handle non-constant delays of index non-blocking assignments.
- $scanf support for real values.
- Fix scheduling of RWsync vs. ROSync callbacks.
- Fix vpi_put_userdata return value.

The iverilog-vpi command now allows .cpp files to stand for C++

Revision 1.52 / (download) - annotate - [select for diffs], Fri Aug 11 13:28:08 2006 UTC (16 years, 9 months ago) by dmcmahill
Branch: MAIN
CVS Tags: pkgsrc-2006Q3-base, pkgsrc-2006Q3
Changes since 1.51: +3 -4 lines
Diff to previous 1.51 (colored)

Update to 20060809 snapshot.  There have been several changes since the
last packaged snapshot.  Those are:

Release Notes for Icarus Verilog Snapshot 20060215

* Part select of memory words should now work according to
  Verilog-2001. This also led to some cleanup of the handling of types
  internally, as well as some infrastructure for general arrays.

* Minor fix to parsing of (* *) attributes.

* Fix rounding of reals to integers.

* Clean up some of the vvp engine related to memories. Remove some
  dead instructions.

Release Notes for Icarus Verilog Snapshot 20060409

the most substantial difference in this snapshot the first signs of
generate support. The compiler now supports generate loops and has
been tested with examples that include wires and gates within the
generate scheme. The regression test suite has very few generate
tests, so any concise self-testing test programs that use generate
would be helpful.

Also, instance arrays that use overridden parameters now work

Task arguments are a bit more flexible in order to support vendor
(notably Xilinx) models that use more interesting task arguments.

Runtime support for bi-directional ports had some bugs fixed, along
with some other minor run-time bugs. Also, the runtime gains support
for typed parameters. And also, there are some new runtime callbacks
for events and memories.

Parameters had a few types related bugs fixed. They are a bit more
flexible now.

And various minor compilation errors have been fixed. This includes
C/C++ compilation errors fixes, and some configure/Makefile tweaks.

Release Notes for Icarus Verilog Snapshot 20060618

Add support for system functions in continuous assignments.

Allow concatenations as arguments to inout ports. This comes with a
small variety of internal part select and concatenation bug fixes.

Fix some bugs in constant propagation through ternary expressions.
Fix broken subtraction if small constants in certain cases.
Fix a few datatype mismatch errors.

Make $readmem give warning when input is inadequate for requested

Fix runtime of nand in continuous assignments.

Fix synchronous user defined primiteves to only follow edges.

Fix a runtime error in some thread delays processing.

Improve limited genvar expression handling.

Start a rework of expression elaboration. Make elaboration aware of
the expression context width when appropriate in order to better
handle expression width and padding.

Fix the make rules for to reflect that they come from the
same source. Fix the to configure the stub target.

Fix portability of the lexor source files on Windows systems. Get rid
of the isatty references.

Make a stub lround when the system version is missing.

* Release Notes for Snapshot 20060809

Some handling of real values is improved. Real valued literals are
handled in net contexts (continuous assignment, etc.). Also, modulus
of real operands now works. (This is an extension to the Verilog

The power operator (**) now works.

Signed right shift works properly now.

The $sscanf and $fscanf are introduced, and work at least for basic
numeric values.

The release function now works to undo general force statements, and
not just contant force statements.

Delay constants up to 64 bits are supported. This at first doesn't
seem like an issue, but when precisions are mixed, it becomes
surprisingly easy to overflow 32bit delays.

The driver is reworked to pass many preprocessor details through a
temporary file instead of on the command line of a system(3)
call. This prevents confusing and incorrect shell processing of
complex strings passed as values to -D flags.

Various other little fixes.

Revision 1.51 / (download) - annotate - [select for diffs], Sun Feb 5 23:08:23 2006 UTC (17 years, 3 months ago) by joerg
Branch: MAIN
CVS Tags: pkgsrc-2006Q2-base, pkgsrc-2006Q2, pkgsrc-2006Q1-base, pkgsrc-2006Q1
Changes since 1.50: +2 -1 lines
Diff to previous 1.50 (colored)

Recursive revision bump / recommended bump for gettext ABI change.

Revision 1.50 / (download) - annotate - [select for diffs], Sun Jan 29 13:53:51 2006 UTC (17 years, 4 months ago) by dmcmahill
Branch: MAIN
Changes since 1.49: +4 -1 lines
Diff to previous 1.49 (colored)

- add missing USE_LANGUAGES (this pkg uses c and c++)
- require gcc>=3.0.  This should fix some recently noted build failures
  on 1.6.* systems.

Revision 1.49 / (download) - annotate - [select for diffs], Wed Jan 25 12:11:00 2006 UTC (17 years, 4 months ago) by dmcmahill
Branch: MAIN
Changes since 1.48: +3 -3 lines
Diff to previous 1.48 (colored)

update to 20060124 snapshot.

A few new features have been added to allow proper simulation with
newer Xilinx UNISIM models. (They are starting to use Verilog 2001
features.) And also various bug fixes in this release.

-- Primitive and continuous assign delays can now be non-constant. This
   needed some new run-time support, so vvp had a slight format change,
   and certain new optimizations follow as a result.

-- Bug handling certain constant sub-expressions in concatenation
   expressions. Also, allow concat expressions in constant contexts.

-- Support for wide divide expressions.

-- Fixes for stubborn compilers.

-- Fix bugs in padding of signed expressions.

-- More fixes for following the data types of expressions.

Revision 1.48 / (download) - annotate - [select for diffs], Sun May 22 20:28:47 2005 UTC (18 years ago) by jlam
Branch: MAIN
CVS Tags: pkgsrc-2005Q4-base, pkgsrc-2005Q4, pkgsrc-2005Q3-base, pkgsrc-2005Q3, pkgsrc-2005Q2-base, pkgsrc-2005Q2
Changes since 1.47: +6 -9 lines
Diff to previous 1.47 (colored)

Replace explicit build dependencies on bison and manipulations on the
YACC variable with USE_TOOLS+=bison.

Revision 1.47 / (download) - annotate - [select for diffs], Sun May 22 20:07:41 2005 UTC (18 years ago) by jlam
Branch: MAIN
Changes since 1.46: +2 -2 lines
Diff to previous 1.46 (colored)

Remove USE_GNU_TOOLS and replace with the correct USE_TOOLS definitions:

	awk		-> gawk
	m4		-> gm4
	make		-> gmake
	sed		-> gsed
	yacc		-> bison

Revision 1.46 / (download) - annotate - [select for diffs], Mon Apr 11 21:45:02 2005 UTC (18 years, 1 month ago) by tv
Branch: MAIN
Changes since 1.45: +1 -2 lines
Diff to previous 1.45 (colored)

Remove USE_BUILDLINK3 and NO_BUILDLINK; these are no longer used.

Revision 1.45 / (download) - annotate - [select for diffs], Wed Dec 1 12:36:21 2004 UTC (18 years, 5 months ago) by dmcmahill
Branch: MAIN
CVS Tags: pkgsrc-2005Q1-base, pkgsrc-2005Q1, pkgsrc-2004Q4-base, pkgsrc-2004Q4
Changes since 1.44: +2 -2 lines
Diff to previous 1.44 (colored)

master site has reorganized a bit

Revision 1.44 / (download) - annotate - [select for diffs], Sat Nov 27 02:50:08 2004 UTC (18 years, 6 months ago) by dmcmahill
Branch: MAIN
Changes since 1.43: +2 -3 lines
Diff to previous 1.43 (colored)

update to verilog-current 20041004.

Release Notes for Icarus Verilog Snapshot 20041004

Some minor Makefile bugs have been fixed, and source file text
formatting has in some cases been normalized for release. Also,
configure scripts have been factored for a more consistent build.

Fixed continuous assignments to carry strength when needed for correct
behavior. This bug led to subtly incorrect reset behavior, but could
have caused strength modeling errors in a variety of situations.

Fixed some <= vs >= behaviors to be consistent. The results of these
comparisons, when sized values are involved, are more standard now.

Revision 1.43 / (download) - annotate - [select for diffs], Sun Oct 3 00:13:13 2004 UTC (18 years, 7 months ago) by tv
Branch: MAIN
Changes since 1.42: +2 -1 lines
Diff to previous 1.42 (colored)

Libtool fix for PR pkg/26633, and other issues.  Update libtool to 1.5.10
in the process.  (More information on tech-pkg.)

Bump PKGREVISION and BUILDLINK_DEPENDS of all packages using libtool and
installing .la files.

Bump PKGREVISION (only) of all packages depending directly on the above
via a buildlink3 include.

Revision 1.42 / (download) - annotate - [select for diffs], Tue Sep 21 02:23:19 2004 UTC (18 years, 8 months ago) by dmcmahill
Branch: MAIN
Changes since 1.41: +2 -2 lines
Diff to previous 1.41 (colored)

update to verilog-current-20040915.  Changes in this snapshot:

The big news is that module instance arrays now work. Gate and UDP
instance arrays have worked for a while, but module instance arrays
were more tricky because of the scope arrys they create. The issues
have been dealt with, and module instance arrays are now supported.

An interesting but subtle set of bugs in the evaluation of ternary
expressions has been fixed. The problems expressed themselves when the
condition expression was constant.

Degenerate wait statements now work properly.

The @* syntax apparently missed sensitivities in l-value expressions
of assignment statements. This led to subtle bugs in carefully crafted
bits of code.

Verilog attributes are properly parsed in a few more contexts. Also,
some specify syntax cases have been fixed.

Some minor spelling and documentation errors have been fixed, along
with assorted compiler warnings.

Revision 1.41 / (download) - annotate - [select for diffs], Thu Sep 2 01:55:47 2004 UTC (18 years, 8 months ago) by dmcmahill
Branch: MAIN
CVS Tags: pkgsrc-2004Q3-base, pkgsrc-2004Q3
Changes since 1.40: +3 -3 lines
Diff to previous 1.40 (colored)

update to verilog-current-20040828

changes include:

Added support for the `default_nettype directine, including the
default net type of "none", which turns off implicit net declarations.

Signed /, % and >>> in nets should now work properly. Also, various
operators of all sorts applied to constants have been improved.

Ranges now work on localparams.

Added the system tasks $unsigned, $is_signed, $mti_random and
$mti-dist_uniform. See the make README.txt for a description of these
system functions. Also, flesh out the standard random number
generators to match the sequences generated by other compilers.

There is now an "sft" file that describes to the compiler the return
value of system functions. This allows user supplied system functions
to have interesting return types. See "SYSTEM FUNCTIO TABLE FILES" in
the iverilog man page. Include a sft file for the system functions,
and move the system functions over to that mechinism.

Fix the behavior of $fgets in tight fitting result buffers.

A variety of compilation environment fixes have been added. These
involve configure scripts and Makefiles.

And of course a variety of other bug fixes, and so on and so forth.

Revision 1.40 / (download) - annotate - [select for diffs], Mon Jun 7 01:09:50 2004 UTC (18 years, 11 months ago) by dmcmahill
Branch: MAIN
CVS Tags: pkgsrc-2004Q2-base, pkgsrc-2004Q2
Changes since 1.39: +2 -2 lines
Diff to previous 1.39 (colored)

update to verilog-current-20040606

* Release Notes for Icarus Verilog Snapshot 20040606

Ports of primitives can bind by name as well as by position. Also
support Verilog 2001 style port declarations for primitives.

System function return types can now be specified by system function
table files. System Function Table Files are described in the iverilog
man page. Also include better system function return types in VPI.

Non-blocking assign of real values to real variables now works.

Properly handle nul strings ("") as 8bit values. This is a weirdness
legacy of XL.

Fix some synthesis problems for logical OR and logical AND. Bitwise OR
and AND were fine. These fixes affected simulation as well.

Handle wait statements with all sorts of constant values. These are
sometimes weird, bug legal.

Handle Negative value reals, and a few other bugs related to real

Change internal use of identifiers to perm_strings for better

Functions returning unsupported types now generate error
messages. Previously, they would quietly generate bad
code. Infrastructure is also added to eventually support arbitrary
function return types.

Better compile-time support for Cygwin vs mingw32.

The ipal target is removed from this source. (ipal is now an add-on
package that is compiled seperately.)

Revision 1.39 / (download) - annotate - [select for diffs], Mon Mar 22 00:15:07 2004 UTC (19 years, 2 months ago) by dmcmahill
Branch: MAIN
CVS Tags: pkgsrc-2004Q1-base, pkgsrc-2004Q1
Changes since 1.38: +2 -2 lines
Diff to previous 1.38 (colored)

add lex to the GNU_TOOLS list.  Needed for SunOS and probably some others.

Revision 1.38 / (download) - annotate - [select for diffs], Fri Mar 12 22:37:12 2004 UTC (19 years, 2 months ago) by dmcmahill
Branch: MAIN
Changes since 1.37: +9 -13 lines
Diff to previous 1.37 (colored)


Revision 1.37 / (download) - annotate - [select for diffs], Tue Mar 2 15:34:07 2004 UTC (19 years, 2 months ago) by drochner
Branch: MAIN
Changes since 1.36: +3 -3 lines
Diff to previous 1.36 (colored)

update to the 20040220 snapshot
changes: bugfixes, VPI extensions

Revision 1.36 / (download) - annotate - [select for diffs], Thu Jan 22 07:21:55 2004 UTC (19 years, 4 months ago) by grant
Branch: MAIN
Changes since 1.35: +2 -2 lines
Diff to previous 1.35 (colored)

replace deprecated USE_GMAKE with USE_GNU_TOOLS+=make.

Revision 1.35 / (download) - annotate - [select for diffs], Mon Aug 25 11:21:50 2003 UTC (19 years, 9 months ago) by drochner
Branch: MAIN
CVS Tags: pkgsrc-2003Q4-base, pkgsrc-2003Q4
Changes since 1.34: +2 -2 lines
Diff to previous 1.34 (colored)

update to the 20030815 shapshot
changes are basically bugfixes, and improvements in the FPGA synthesis

Revision 1.34 / (download) - annotate - [select for diffs], Thu Jul 17 21:25:27 2003 UTC (19 years, 10 months ago) by grant
Branch: MAIN
Changes since 1.33: +2 -2 lines
Diff to previous 1.33 (colored)


Revision 1.33 / (download) - annotate - [select for diffs], Mon Jul 14 09:51:48 2003 UTC (19 years, 10 months ago) by drochner
Branch: MAIN
Changes since 1.32: +6 -2 lines
Diff to previous 1.32 (colored)

update to snapshot "20030705".
There was a couple of snapshots since february; besides bugfixes the
major highligths might be:
-handling of real values at various places
-support for library modules (esp cadence PLI1)
-better FPGA support (esp Virtex II)
-"vvp" interactive mode added

Also converted to buildlink2, and dependencies to libz, libbz2 and
readline added.

Revision 1.32 / (download) - annotate - [select for diffs], Tue Feb 4 00:46:07 2003 UTC (20 years, 3 months ago) by dmcmahill
Branch: MAIN
CVS Tags: netbsd-1-6-1-base, netbsd-1-6-1
Changes since 1.31: +4 -7 lines
Diff to previous 1.31 (colored)

update to verilog-current-20030202.

This is the first packaged (in pkgsrc) snapshot after the verilog-0.7

This snapshot adds preliminary support for real variables to the language
to the features already found in verilog-0.7.

Revision 1.31 / (download) - annotate - [select for diffs], Tue Oct 22 02:52:17 2002 UTC (20 years, 7 months ago) by dmcmahill
Branch: MAIN
Changes since 1.30: +2 -3 lines
Diff to previous 1.30 (colored)

update to verilog-current-20021019

Release Notes for Icarus Verilog Snapshot 20021019

The synthesizer now detects asynchronous set/reset inputs to DFF
devices. The fpga and vvp code generators have been updated to support
these signals.

The vvp code generator also gained some register management code that
improves the thread register usage. This redoces code size for certain
common cases, and thus improves simulation performance.

The requirements on `ifdef and related compiler directives has been
relaxed, to correspond to more common behavior.

The parameter range support crashed if the range expressions had
parameters in them. This is fixed, and some signed-ness bugs fixed
along with it.

Rearrange some of the configure script tests to assure better
compatibility accross platforms.

Revision 1.30 / (download) - annotate - [select for diffs], Thu Oct 17 01:38:42 2002 UTC (20 years, 7 months ago) by dmcmahill
Branch: MAIN
Changes since 1.29: +2 -1 lines
Diff to previous 1.29 (colored)

fix the iverilog-vpi shell script (bash-isms)

Revision 1.29 / (download) - annotate - [select for diffs], Sun Oct 13 23:01:27 2002 UTC (20 years, 7 months ago) by dmcmahill
Branch: MAIN
Changes since 1.28: +2 -2 lines
Diff to previous 1.28 (colored)

update to verilog-current-20020921 snapshot.  Many improvemnts in the
synthesis code and bug fixes in the simulation code since the last
packaged snapshot.

Revision 1.28 / (download) - annotate - [select for diffs], Thu Aug 29 11:15:56 2002 UTC (20 years, 9 months ago) by dmcmahill
Branch: MAIN
Changes since 1.27: +2 -2 lines
Diff to previous 1.27 (colored)

update to verilog-current-20020828

Release Notes for Snapshot 20020828

This snapshot adds support for parameter and localparam bit
ranges. This is a IEEE1364-2001 feature, although some -1995 compilers
have supported it in the past.

Fixed a *nasty* and slippery bug with the evaluation of bit select of
nets. (Bit select of variables was unaffected.) The symptoms did not
clearly point to the problem, so bugs related to it were often mis-

Gate delays were lost when constants were propagated to their
inputs. This is fixed for the known broken cases. Also, mux output
delays have been fixed. Also, release statements that apply to elided
nets are turned into no-ops.

The r-values of non-blocking assignments are now precalculated at
compile time, if possible, as is done with blocking assignments. This
speeds up constant propagation, and is more thorough.

Also optimize subtraction of small constants from vectors, with the
new %subi instruction in vvp. This saves some in code size and thread

Handling of x in r-value bit selects and memory word selects did the
wrong thing. Now they do the right thing. Also, x in the selector of
?: ternary operators does the right (and complicated) thing now. In
the process, a fork-join code generator bug was fixed.

Several bugs with time formatting have been fixed.

Temporaries in sequential blocks are detected by the synthesizer, and
converted into wires when needed. This expands support for
combinational logic synthesis.

Revision 1.27 / (download) - annotate - [select for diffs], Sat Aug 24 04:36:44 2002 UTC (20 years, 9 months ago) by dmcmahill
Branch: MAIN
Changes since 1.26: +2 -2 lines
Diff to previous 1.26 (colored)

update to verilog-current-20020817.  Many many changes and bug fixes
since the last packaged snapshot.  Better language coverage, better
performance, improved synthesis, fixed bugs.  Too much to list here.

Revision 1.26 / (download) - annotate - [select for diffs], Tue May 7 00:11:20 2002 UTC (21 years ago) by dmcmahill
Branch: MAIN
CVS Tags: pkgviews-base, pkgviews, netbsd-1-6-RELEASE-base, netbsd-1-6, buildlink2-base, buildlink2
Changes since 1.25: +2 -2 lines
Diff to previous 1.25 (colored)

update to verilog-current-20020505

many improvements and bug fixes since the last packaged snapshot including:

-added the $sizeof system function as a builtin
-In VPI, the simulator event callbacks now work
-Concatenation expressions in parameters were broken are broken
-added the vpiModule iterator to VPI scope handles

Revision 1.25 / (download) - annotate - [select for diffs], Thu Mar 28 03:07:29 2002 UTC (21 years, 2 months ago) by dmcmahill
Branch: MAIN
CVS Tags: netbsd-1-5-PATCH003
Changes since 1.24: +4 -3 lines
Diff to previous 1.24 (colored)

update to verilog-current-20020317

Release Notes for snapshot 20020317

The first difference in this snapshot from the 0.6 release is that vvm
is no longer compiled by default. If you want to compile vvm, you must
enable it at configure time (--enable-vvm) and rebuild from
scratch. Eventually, vvm will disappear from the release altogether.

The next major difference is new support for user defined
functions. It is new support, so it is bound to be buggy, but it
should be somewhat complete. The major problem has been solved, so all
that remains are bugs around the edges.

The vvp run-time scheduler has been changed slightly. The run time
behavior is getting increasingly precise and picky, as larger designs
are thrown at the compiler. The change introduced in this snapshot
fixes logic gates to not propagate zero-time pulses, and thus fixes
some weird bugs in large designs.

I've also added initial support for the Verilog 200x pragma comment,
which are (* *) pairs. For now, the compiler ignores them as
comments. This is what a compiler is supposed to do with anything that
is not specifically recognized.

Also, Tony (Anthony Bybell) has added LXT dump support. The LXT output
file is a waveform output format that is much more compact then VCD.
The gtkwave waveform viewer supports the LXT format, and should
operate a bit faster when viewing LXT files. For now, there are
separate system tasks for managing LXT output ($lxt_dumpvars, etc) but
eventually the dump format will be selectable by environment variable
or command line switch.

This snapshot also includes various random bug fixes and improved
error messages for incorrect code.

Revision 1.24 / (download) - annotate - [select for diffs], Wed Jan 16 19:33:18 2002 UTC (21 years, 4 months ago) by dmcmahill
Branch: MAIN
Changes since 1.23: +9 -3 lines
Diff to previous 1.23 (colored)

update to verilog-current-20020112

many many changes since the last packaged snapshot.

A brief sampling of the changes (which include many bug fixes and
enhancements) is:

A variety of little problems with $display format strings have been

The % operand should now simulate properly. Also, the * operator is a
little bit more optimized, and works in constant expressions.

Several bugs in strength modeling have been fixed. This includes drive
strengths on continuous assignments, which in the past generated code
without the strengths. Also, vvp gained some missing support for
constants with strength. I think that strength modeling is now

vpi_get_vlog_info support has been added to the vvp run-time. This is
a PLI function that allows access to run-time command flags. Also, vpi
access to root modules now works properly.

Revision 1.23 / (download) - annotate - [select for diffs], Sat Dec 15 18:43:37 2001 UTC (21 years, 5 months ago) by dmcmahill
Branch: MAIN
Changes since 1.22: +3 -3 lines
Diff to previous 1.22 (colored)

update to verilog-current-20011209 snapshot.

Many changes since the last packaged snapshot.  A sampling of these are:

Support for hierarchical names has been largely rewritten. The major
consequence of this is that escaped names now have much better
support. By now, most any combination of escaped and hierarchical name
should work properly, for nets, parameters, and anything else.

Output delays for primitive gates, including user defined primitivies,
should now work properly. Delays on nets still do not work, although
the parser now parses them and prints a "sorry" message.

Bugs in support for division(/) and modulus (%) have been fixed.

Bugs in l-values of synthesized DFF devices have been fixed. These
bugs were related to part selects of vectors in l-values.

A few XNF code generator bugs and limitations were fixed.

And as usual, a variety of miscellaneous bugs have been fixed in this

The bit size of the results of some unary redunction operators is now
properly handled. Also, similar problems with logical functions have
been fixed.

force/release now works for variables, though not yet for
nets. Assign/deassign already work.

many other bugfixes

Revision 1.22 / (download) - annotate - [select for diffs], Wed Oct 24 12:27:11 2001 UTC (21 years, 7 months ago) by dmcmahill
Branch: MAIN
Changes since 1.21: +10 -6 lines
Diff to previous 1.21 (colored)

update to verilog-current-20011020.

changes since last snapshot include:

- addition of a fpga target for synthesis.  outputs edif, optimized for
  xilinx virtex parts.
- fixed bug with synthesis of !=
- fixed bug in hex constant parsing
- fixed vvp bug with subtracting very wide words
- much improved VCD output
- many other bug fixes and robustness improvements.

Revision 1.21 / (download) - annotate - [select for diffs], Thu Sep 27 23:17:47 2001 UTC (21 years, 8 months ago) by jlam
Branch: MAIN
Changes since 1.20: +2 -2 lines
Diff to previous 1.20 (colored)

Mechanical changes to 375 files to change dependency patterns of the form
foo-* to foo-[0-9]*.  This is to cause the dependencies to match only the
packages whose base package name is "foo", and not those named "foo-bar".
A concrete example is p5-Net-* matching p5-Net-DNS as well as p5-Net.  Also
change dependency examples in Packages.txt to reflect this.

Revision 1.20 / (download) - annotate - [select for diffs], Tue Jul 3 18:23:46 2001 UTC (21 years, 10 months ago) by dmcmahill
Branch: MAIN
Changes since 1.19: +3 -2 lines
Diff to previous 1.19 (colored)

update to 20010630 snapshot.

changes are:

I've done some cleanup of the mingw port of Icarus Verilog. I've also
added instructions for how to build Icarus Verilog under mingw. I'm
working on making that the preferred way to support Windows, and when
I make the 0.5 release I will make Windows binaries this way. Anyhow,
feedback on the build instructions and the build results using the
instructions in mingw.txt are welcome.

I've make "vvp" the default target type. The older vvm behavior is
available with the "-tvvm" flag to iverilog, but I would rather be
told about (and fix) bugs in the vvp code generator and run time.

I've added support for the (unsigned) right shift operator. The left
shift has been working for a while now, but right shift somehow
slipped through the cracks. The shift operators still don't quite work
in structural contexts, but they should show up sometime next week.

I've finally got VCD output working properly with vvp. It may even be
better then with vvm, although some internal symbols are still generated.

A few odd bugs have been fixed, including a code generation error for
xnf, and error checking of user defined function parameters.

Revision 1.19 / (download) - annotate - [select for diffs], Mon Jun 11 06:34:20 2001 UTC (21 years, 11 months ago) by jlam
Branch: MAIN
Changes since 1.18: +1 -2 lines
Diff to previous 1.18 (colored)

CPPFLAGS is now passed to MAKE_ENV and CONFIGURE_ENV by, so
adapt by moving CPPFLAGS settings to top-level, and removing explicit
inclusion of CPPFLAGS into MAKE_ENV and CONFIGURE_ENV.

Revision 1.18 / (download) - annotate - [select for diffs], Mon May 21 22:25:19 2001 UTC (22 years ago) by dmcmahill
Branch: MAIN
Changes since 1.17: +3 -3 lines
Diff to previous 1.17 (colored)

update to verilog-current-20010520.

many changes since the last snapshot.  Mostly they involve expanded
VVP support.  The VVP target now passes >200 of the tests from the
test suite.  While not as complete as the VVM target, VVP is getting
closer and its _much_ _much_ faster.

Revision 1.17 / (download) - annotate - [select for diffs], Sat Apr 28 03:15:26 2001 UTC (22 years, 1 month ago) by dmcmahill
Branch: MAIN
CVS Tags: netbsd-1-5-PATCH001
Changes since 1.16: +3 -3 lines
Diff to previous 1.16 (colored)

update to verilog-current-20010422

Changes since the last packaged snapshot from the authors announcements:

Icarus Verilog snapshot 20010422
I've integrated a bunch of UDP patches from Stephan Boettcher. These
go to the core of ivl, so if you use Icarus Verilog with UDPs, you
might want to give this a test for us.

Stephan has also added some ivl_target support for UDP devices. This is a
prerequisite to vvp support for UDP devices.

Some of you have been beating me over the head about disable, so the
vvp target now supports disable. It only works in certain very constrained
situations, but the idea is there and the more common cases are simply a
matter of getting around to them. I actually could use more examples of
the use of disable for the test suite.

In the process, I have settled on the interaction of threads and scopes,
and changed the %fork syntax to match. See the README.txt and opcodes.txt
file for details. The implementation of %end and %join simplified in
the process.

The vvp-tgt code generator supports a few more gate types. New gate
types are pretty easy to add, it's just boring grunt work. That's why
they've been popping up slowly.

I've also got certain behavioral shifts working. Only constant shifts,
so far, but this covers a pretty large percentage of the real world
uses of shift, I think.

I fixed a few specify block parse problems, so it should ignore
even more complex specify blocks now:-) One of these days I really will
properly support specify blocks.


I was hoping to get vvp up to a similar level as vvm by the end of
April, but that doesn't look like it's going to happen. I'm up to 182
tests passed, compared to 318 of Icarus Verilog/vvm, so I have a ways
to go yet. I see no real point to making a release until I get up to
300 or so tests passed. That is the goal for 0.5 release.

But of course if vvp is enough for you, then it is soooo much faster
then vvm.

Icarus Verilog 20010415 Snapshot
As with all the most recent snapshots, this is almost entirely progress
with the vvp code generator and simulation engine. I'm up to 159 tests
passed in the test suite, so I'm getting there. But there's still plenty
to go.

I also fixed what appeared to be a minor problem with elaboration of ?:
expressions in continuous assignments. The code was actually fine, it
was a spurious assert. This fix affects vvm as well.

Icarus Verilog/vvp now support <= statemements with internal delays.
That is, "foo <= #10 bar;" should work properly, and there are tests
in the suite that prove it. This is a pretty common syntax, so this
should help a lot of folks.

I also fixed a bug in the code generator that would cause it to put a
constant bit as a destination for the bitwise boolean operators. This
caused run-time asserts.

The event or support in vvp has been extended to now support arbitrary
width, so now you can for example wit for any changes in a 32bit reg.
This handles most of the likely cases, so @ statements should now be
pretty generally functional.

The handling of run-time threads has been revamped in preparation for
support of the disable statement. It also plugs a memory leak where
fork/join and task/function calls are invoked. And this version should
also clean up all those tiny initial foo=bar threads that all programs
seem to have. Threads that are done are now freed, along with their
memory, hopefully reducing the runtime memory footprint.

That's pretty much it this time 'round. Working with threads took some
time, so the progress isn't as flashy as it sometimes is.

There is still lots to do with vvp before 0.5, but I would appreciate
any feedback you can offer. It's complete enough already that I'm able
to accept bug reports on it, even if it turns out to be a "not supported
yet" type of thing. At this point, I'd be curious to know what hangups
are preventing its regular use.

Revision 1.16 / (download) - annotate - [select for diffs], Sat Apr 14 14:47:29 2001 UTC (22 years, 1 month ago) by dmcmahill
Branch: MAIN
Changes since 1.15: +3 -3 lines
Diff to previous 1.15 (colored)

update verilog-current to 20010407

changes since last snapshot are (from the authors email)


Still more progress on the new VVP simulation engine:

As with last week, this snapshot includes a lot of work on the ivl_target
API in support of code generation for vvp. Also, the vvp execution engine
has progressed some.

In fact, vvp has grown up to understand signed vectors and some signed
expressions. The signed vectors are mostly for VPI use, the signed
comparison instructions actually do signed work. Case comparisons are
new, along with %and and %or instructions, and %nor/r for reduction.
I also added a few new gate types to the .functor support.

A bug in the propagation of values by %set instructions has been fixed.
Specifically, the %set instruction not only sets the value of the .var
that it references, but also executes the propagation events that result.
This fixed some event ordering bugs.

Some VPI support needed by system.vpi is added to vvp to allow it to
properly handle signed signals, decimal values, and a few other details.
$display should work much better then it did last week.

Back in the vvp.tgt code generator, lots of new stuff is happening.
Several of the bitwise binary operators have been added, as well as
more comparison operators. This includes handling of signed expressions.
This also implies that vvp.tgt generates the proper .net vs .net/s
and .var vs .var/s statements.

User defined functions and tasks are now working. In fact, the vvp
target probably handles more functions (in behavioral code) then the
vvm engine. I've received several bug reports about user defined functions
with loops, that don't work under vvm. These should work with vvp.

Non-blocking assignments now work, too.

All forms of case/casex/casez are supported by the code generator, and
use the proper compare instructions. Forever, Repeat and While loops
also work now. A few bugs in event handling, and all the edge types
(including behavioral triggers) should work with limitations. Event or
is still in the works, and any-edge of large vectors (>4 bits) does not


As you can see, a *lot* of stuff is happening. I'm up to passing 110+
tests in the regression test suite (Icarus Verilog/vvm passes 318 tests)
so the changes are actually making things work. Test and be merry!

More and more progress on VVP. More and more snapshots.

A lot of work has been done to the ivl_target loadable target API.
This API is growing to support the also growing tgt-vvp target. I've
added support for case statements, event triggers fork blocks.

Of course this also means that the tgt-vvp code generator and the
vvp simulator now support constructs including case, events, and
parallel blocks.

I've also fixed up the driver to properly report errors that tgt-vvp
detect. This makes the test suite regression script work a lot better.

I'm up to more then 70 tests in the test suite passing. I'm finding
that writing the code generator for vvp assembly is a *lot* easier
then writing a code generator for C++/vvm. Fortunately, the vvp
assembler is pretty fast.

At any rate, the vvp simulation engine is starting to show signs of
being useful. It still does not cover nearly as much of Verilog as
vvm, but what it does cover is so much faster that it may be worth
your while to try it out. And more eyes looking at it can only be a
good thing.

Revision 1.15 / (download) - annotate - [select for diffs], Wed Apr 11 13:38:41 2001 UTC (22 years, 1 month ago) by wennmach
Branch: MAIN
Changes since 1.14: +2 -2 lines
Diff to previous 1.14 (colored)

Use wildcards in CONFLICTS.

Revision 1.14 / (download) - annotate - [select for diffs], Sat Mar 31 00:00:35 2001 UTC (22 years, 2 months ago) by dmcmahill
Branch: MAIN
Changes since 1.13: +3 -3 lines
Diff to previous 1.13 (colored)

update to verilog-current-20010324.  Changes since the last version from
the authors announcement are:

There are a few bugs in the main compiler that are fixed. There has
also been an extension to the $fopen that adds support for opening
files for reading. The $fgetc has been added to take advantage of this.
This was done on the VPI side, although a slight extension to the mcd
functions was created.

The real news is the vvp simulation engine. I've added the tgt-vvp
code generator source and the vvp assembler/simulator, and the combination
actually produces the occasional working program. And it makes them
very quickly. So far as I can tell now, I am going to be very pleased
with the final outcome when this work is complete. However, it is not
at all ready to use. This snapshot is mostly to give a preview of things
to come to a wider audience.


If you are accustomed to the existing vvm behavior, you remember that
the vvm simulator works by generating C++ and feeding that to the g++
compiler. Many of you are painfully aware of that.

VVP does *not* work like that. Instead of generating C++, the
generator emits assembly language for an abstract simulator processor.
The processor that the assembly targets doesn't really exist, but the
vvp program, included in this Icarus Verilog snapshot, assembles the
code to data structures in memory, then efficiently emulates the abstract

So the simulation of a program via vvp works by first compiling the
Verilog to vvp assembly. The vvp.tgt modules generates the code, and
is envoked when you use the ``-tvvp'' switch to iverilog.

The vvp assembly file so created is then passed to the vvp program to
be assembled and executed. There is a single vvp input file that is the
design to simulate. The vvp assembler is designed to execute the design


The ivl_target.h header file describes the loadable target API that
the vvp code generator uses to gain access to the design. Then the
tgt-vvp directory contains the implementation of the vvp code generator.

The vvp directory contains the implementation of the assembler/simulator
that runs the compiled design. The README.txt file describes how the
vvp program works in general, and points to other txt files. There are
a variety of other .txt files in the vvp directory that describe how
the major components of the vvp program work.

Revision 1.13 / (download) - annotate - [select for diffs], Tue Mar 27 03:19:47 2001 UTC (22 years, 2 months ago) by hubertf
Branch: MAIN
Changes since 1.12: +3 -3 lines
Diff to previous 1.12 (colored)

Change BUILD_DEPENDS semantics:
first component is now a package name+version/pattern, no more

While there, introduce BUILD_USES_MSGFMT as shorthand to pull in
devel/gettext unless /usr/bin/msgfmt exists (i.e. on post-1.5 -current).

Patch by Alistair Crooks <>

Revision 1.12 / (download) - annotate - [select for diffs], Fri Feb 16 13:46:30 2001 UTC (22 years, 3 months ago) by wiz
Branch: MAIN
Changes since 1.11: +2 -1 lines
Diff to previous 1.11 (colored)

Update to new COMMENT style: COMMENT var in Makefile instead of pkg/COMMENT.

Revision 1.11 / (download) - annotate - [select for diffs], Sun Jan 14 19:01:13 2001 UTC (22 years, 4 months ago) by dmcmahill
Branch: MAIN
Changes since 1.10: +3 -3 lines
Diff to previous 1.10 (colored)

update to verilog-current-20010113

bug fixes and signed support (yay!).

detailed changes since last packaged snapshot from the
authors announcements:

Icarus Verilog snapshot 20010113
We're getting close to release candidates. Maybe another snapshot, then
I start with making 0.4 release candidates. So lets get this tested so
that I can move forward!

This snapshot largely fixes a whole bunch of bugs. I'm working feverishly
to catch up to the reported bugs, but they are coming in about as fast
as I can resolve them. (Not that I'm complaining, mind you. These PRs
are really helping me make it better.) But that means I'm going to just
concentrate on getting as many PRs done as I can before the release.

The syntax of functions and tasks has been expanded to allow parameters.
This is not a common thing to do, but someone puts parameters if functions

The syntax of functions and tasks has been expanded to allow parameters.
This is not a common thing to do, but someone puts parameters if functions
so I had a PR to fix:-) Also I caught a problem with executing functions
that take no input parameters. In fact, a bunch of function related bugs
were fixed. I lost track of em all.

Ports of tasks weren't elaborated properly. I fixed this and a few related
problems so most legal l-values should work as task port expressions now.
Memories within tasks should also work properly now.

Speaking of ports, I now report errors when there is a port direction
for module ports that don't exist. In fact, there are a whole bunch of
cases where I've added required error messages.

The %d format of display strings now displays signed negative values as
negative values instead of the unsigned equivalent. This goes along with
the other signed arithmetic features from the -2000 standard that are now

I fixed up the Makefiles (thanks to a contribution) to support build using
the VPATH capabilities of the makefile. You should be able to compile for
multiple targets now from a shared source directory.

Icarus Verilog snapshot 20010106
I'm just managing to barely keep up with the bug reports arriving in
the bug tracking system. I'm pleased with the success of the ivl-bugs
robot. These bug reports have allowed me to better manage and record
progress. Keep those bug reports coming!

I've added support for arrays of integer and time variables, as well
as the Verilog 2000 initialization syntax for these types. I have also
made some internal changes to integer support. Integers are now just
a shorthand for ``reg signed [31:0]'' and signed variable support has
made some internal changes to integer support. Integers are now just
a shorthand for ``reg signed [31:0]'' and signed variable support has
been generalized. This makes it easier on the code generators, as they
do not need to know that a variable was a integer, a time, a foo or a bar.

I few constant propagation errors have been fixed. Continuous assignments
of constants to nets should behave correctly now.

Many people noticed lack of expression support for parameters. In fact,
the problem was a lack of support for a bunch of specific operators. I've
added many operators. This has the side effect of improving constant
propagation as well, in some cases finding more dead code to eliminate.
This also affected expressions that were index expressions of memories
and vector declarations.

The / operator in continuous assignment expressions is fixed. There were
a few size related issue here that are now fixed.

I've added to the i3331364-notes.txt file a clarification of my position
on parse of repeat statements. This position is compatible with XL behavior.

Passing parameters to user defined functions in behavioral code was pretty
darn broken. I managed to fix this. You can tell that not many people use
user defined functions:-)  (It doesn't help that Icarus Verilog is picky
about them.)

For vvm, I've put some effort into optimizing the compile time of programs
by reducing the size of the output code. I've reduced redundancies some,
and used loops to handle vectors where possible.

A few bugs related to $dumpvars were cleaned up. Function scopes work.

Revision 1.10 / (download) - annotate - [select for diffs], Tue Dec 19 18:53:51 2000 UTC (22 years, 5 months ago) by dmcmahill
Branch: MAIN
Changes since 1.9: +6 -3 lines
Diff to previous 1.9 (colored)

update verilog-current to 20001216.

Changes since the last packaged snapshot are (from the authors announcements):

Icarus Verilog snapshot 20001216
This is the last snapshot before the holidays, so I hope it has your
favorite present in it. A lot of PR#s have been dealt with, and for a
brief moment I felt like I was getting ahead of the pending list:-)

I've added support for non-integer times, at least in a few contexts.
The `timescale directives should interact properly with the decimal
point in delays, causing more accurate timing simulations. This should
make vendor-supplied libraries work much better.

I've added support for signed reg variables. Signed expressions should
now generally do the right thing, but this feature needs much more testing,
and many more tests in the test suite. However, I do know that signed
comparisons should work properly. Bug reports for problems with signed
arithmetic are encouraged.

Many people have been having troubles with Cygwin compilation. The
problem was with the latest version of binutils. Venkat came up with a
solution that works with old and new binutils, so you can now compile
with the very latest cygwin software. This should make things a lot
easier for a lot of people.

I've made initial steps toward an HP/UX port. The configure script should
detect the right dl library to use, and the t-dll target should be able
to load loadable targets. I am looking for a volunteer to take responsibility
for the HP/UX port as I have no suitable machines. Said person should
be able to compile Icarus Verilog, manage HP/UX specific portability
issues, and be able to make precompiled packages when the stable release
is out.

I'm still looking for a similar volunteer for FreeBSD/{alpha,i386}.

Some more progress was made on support for PALs. I'm close to choosing
macrocell modes and configuring fuses. Won't be long now, folks.

Icarus Verilog snapshot 20001129
few more constant propagation improvements this time, most notably
XOR an XNOR are now fairly complete. These are interesting as they are
generated by comparison operators so show up pretty often. And it is
common to compare numbers to constants. Thus, there are lots of oppor-
tunities for gate elimination!

Synthesis of unary ! now works. Unary ~| (reduction nor) should also
be in good shape now, as should binary || (logical or). Synthesis of
binary && is still a little shaky. Go ahead and file reports if you
trip on it. Binary != was broken with XNF synthesis, so that is also
fixed, along with a few cases of mangled XNF output. And there were
also a few bugs related to the CE of inferred DFFs, that didn't get

A *big* problem with synthesis occurred with non-blocking assignment.
Icarus Verilog simply failed to synthesize the r-value of the assignment
and all kinds of bad things happened. I fixed this, it's better now.

Whew! Lots of XNF synthesis bugs fixed! This is what happens when users
take the time to submit good bug reports.

There are also some bugs related to dead signal elimination that causes
Icarus Verilog to crash in some synthesis cases. These have been fixed
up so far as I know.

I have slightly improved root module detection of iverilog. If there is
only one module in a source file, it is pretty obvious that it is the root
module, even if it has ports. This is a common case for XNF synthesis
(especially when making small macros with Icarus Verilog) and should save
some typing and confusion.

Revision 1.9 / (download) - annotate - [select for diffs], Fri Nov 24 18:03:58 2000 UTC (22 years, 6 months ago) by dmcmahill
Branch: MAIN
Changes since 1.8: +3 -3 lines
Diff to previous 1.8 (colored)

update to verilog-current-20001119

changes since the last packaged version (from the authors announcements):

Icarus Verilog snapshot 20001119
The big change here (code wise) is improved and corrected constant
propagation. I was missing OR, NOR, NAND and XOR propagations, and
got some of the AND calculations wrong. This fixes this shortcoming
and in some cases this actually may speed up your compile a tiny bit.
Some more dangling signals are also eliminated.

supply nets are now working (PR#17). They also will trigger constant
propagation (as they have constant values) in certain cases.

Those of you doing cygwin compiles have trouble compiling I've
put into the cygwin.txt some slightly better instructions for dealing with
this situation, when it comes up.

I've also added missing symbols to ivl.def, so that tgt-stub properly

Icarus Verilog snapshot 20001112
This snapshot includes support for MOS et al devices as contributed
by Tim Leight. It appears to actually work as advertised, and I also
have from him a collection of tests that I'll be adding to the test
suite as soon as I get copyright information from him. So if you have
been dreaming of simulating MOS devices with Icarus Verilog, give this
a try. This update also fixed PR#27.

I've also cleared up a few bugs related to unconnected module ports.
Module port syntax is pretty byzantine, as PR#38 shows.

The loadable target API has gained access to flip-flops. This is required
for PLD code generation to work. I think the ivl_target API now supports
the minimum devices needed to generate PLD files, and I'm on to the task
of getting ancillary PAL support working.

Icarus Verilog snapshot 20001104
Yes, I've managed to find the right bits to get Icarus Verilog to compile
on RedHat 7.0, and this snapshot includes those fixes. It took some back-
and-forth with tech support at RedHat to get it going.

I've also fixed up make check so that it works in general. If you use
"make check" after building, the makefile will run the examples/hello.vl
program through the local parts to make sure they minimally work.

I've added support for the "time" data time and more complete support
for the $time system function. These should work properly in all cases
now, so cases of not working are worthy of a bug report.

I've also integrated a re-implementation of sequential UDPs from Stephan
Boettcher, so I would appreciate it if all you folks using primitives
give this a fresh test. (It should be an improvement.)

This is a relatively small message, which doesn't reflect the complexity
of the changes. The "time" support in particular caused a lot of threads
to be pulled. Also, I've been doing some PLD stuff on the side, so I've
been busy.

I've also knocked of PR#11, 14, 33, 34, 39 and a few other bugs.

Revision 1.8 / (download) - annotate - [select for diffs], Fri Oct 27 03:59:47 2000 UTC (22 years, 7 months ago) by dmcmahill
Branch: MAIN
Changes since 1.7: +3 -3 lines
Diff to previous 1.7 (colored)

update to 20001021 snapshot of verilog-current

from the authors announcement:

The loadable target module API is starting to take shape.

That is the major thrust nowadays with Icarus Verilog, after all, so
progress is being made here. The biggest change is in fact a philosophy
change. The target module now needs only a single symbol -- target_design --
to receive the whole design. The target module can from there and using
the API access the entire design randomly. So if you wanted to implement
a graphical browser, you could:-)

I've added support for the l-values of procedural assignments, and also
back pointers to objects that reference ivl_nexus_t objects. This closes
the loop so that there should be no dead-ends in the design.

I've clarified and expanded the descriptions in the ivl_target.h header
file. There should be just about enough documentation to properly used
all the various types. (Have any of you tried to write GIMP plug-ins?
Have you looked at the libgimp header files? Have you seen any comments
there?-( I won't ever sink to that level, I hope.)

I've also imtegrated updates to the Cygwin32 port to support loadable
targets under Cygwin32. After much struggling, Venkat managed to discover
the secret magic needed to get load time symbol binding to work. Hopefully
I didn't break it too bad when I changed the API again. (I think it is
still fine.)

Revision 1.7 / (download) - annotate - [select for diffs], Sun Aug 6 15:43:34 2000 UTC (22 years, 9 months ago) by dmcmahill
Branch: MAIN
CVS Tags: netbsd-1-5-RELEASE, netbsd-1-4-PATCH003
Changes since 1.6: +3 -3 lines
Diff to previous 1.6 (colored)

update to verilog-current-20000805.  Changes since the last packaged snapshot
are (from the authors announcements):

Icarus Verilog snapshot 20000721
(first snapshot after the 0.3 release)

This snapshot adds no new features or language support, but is working
towards more precise interpretation of scheduling and value propagation

The first thing I've done is redesign the internal Link structure that
is used to connect the internal netlist together. There are some aspects
of the nexos of a set of links that were carried by the Link class or
by external functions. These have been moved to the new Nexus class and
linking and structure has improved because of it.

This has led me to modify the handing of signal initial values. In practice,
the time-0 value of a net is a property of the nexus instead of the objects
that are connected together, so I have implemented it so, and in the
process fixed a bunch of initial value problems.

One new feature that is added is support for non-constant delay expressions.
Now, you can even have something like ``#($random%256) <statement>'' and
expect it to do what you think. (So now the telephone example in James
Lee's "Verilog Qickstart" actually works!)

I've added some missing support for various operators in constant expressions.
I've also added some more of the friends of $random for those folks who
do stochastic modeling.

Constant propagation carries some new bug fixes, and some new smarts. It
is for example able to detect a mux with a constant 'bz input and replace
it with bufif devices, and other clevernesses with logic reduction.

Icarus Verilog snapshot 20000729

Like I said, the `timescale compiler directive now more or less works.
You can now specify timescale for modules, and the compiler will figure
out a global design resolution and scale your time values to match. The
VCD dumps should reflect the chosen resolution automatically. Floating
point notation is not yet supported, we'll see if that turns out to be
a problem.

A problem with `timescale support is that the compiler will allow unitless
modules. This can happen if you have `timescale late in the source file.
The default unit is the not-very-intuitive 1s. Frankly, I don't like the
`timescale semantics for this sort of reason, but its an accepted
standard, so I'm stuck with it.

I've also added support for min:typ:max expressions. The compiler chooses
one of the three expressions at compile time, based on a compile time
switch. You can ask for min typ or max values via the "-Tmin" etc. switch
to the iverilog command. If you do not specify a switch, the compiler will
choose the typ values but print warnings. The -Ttyp switch will suppress
the warnings.

I have fixed yet more net initialization bugs. These are getting pretty
subtle, now, so you should have a hard time tickling any remaining errors
here. I've also fixed a nasty and subtle bug in event expression support.
This bug only happened when the design had many event expressions with
many conjunctions.

Although they are not ready for use, I have made some forward progress
with disable statements. I now at least elaborate them, so now I just need
to figure out how to make the run-time work out. That's the hard part,
I'm afraid.

Icarus Verilog snapshot 20000805
I've finally dealt with a problem that's been nagging at me for a while.
Until now, it has been possible that excessively clever hierarchical
references into and out of task scopes could confound symbol lookup.
I think I finally put that to rest, and in the process reorganized the
netlist format for holding task definitions. It should no longer be
possible to confuse name binding in Icarus Verilog.

Found and fixed a silly bug in elaborating  e?a:'bz and e?'bz:a expressions
into bufifN devices. I got the sense of the enable wrong in one of the
cases. All fixed (and the test suite updated to catch this silly mistake:-)

tri0 and tri1 nets should now work properly. These are mostly a run-
time issue which I solved using resolution functions. This is actually
a technique that I borrowed from VHDL.

For those of you doing XNF synthesis, I fixed up my FF/RAM detector to
allow <= assignments in always blocks. This is in fact the preferred way
to describe DFFs as <= more accurately simulates their RTL nature.

Also found and fixed a few DOS \r\n line end issues in the lexical ana-
lyser and the preprocessor. We sometimes forget how tricky these line-
end problems can be, and compiler directives are the most susceptible.
This problem most likely occurs when you transport files from a DOS
environment. (The MAC folks haven't complained much, so either I got it
right for them, or Kato took care of the problems for me:-)

Revision 1.6 / (download) - annotate - [select for diffs], Tue May 30 23:43:43 2000 UTC (23 years ago) by dmcmahill
Branch: MAIN
Changes since 1.5: +3 -3 lines
Diff to previous 1.5 (colored)

update to verilog-current-20000527

changes since last packaged snapshot are (from the authors announcements):

Icarus Verilog 20000527 Snapshot

It's snapshot time!


This snapshot doesn't add any new features, but fixes a few bugs. I've
taken care of a bunch of bug reports with an eye towards getting this
polished up for a 0.3 stable release.

I fixed some problems with elaborating the condition expression of a
ternary operator. This was a long-standing bug that only happened in
structural (i.e. continuous assignment) situations.

I've also done some merging of event expressions. The netlist format makes
NetEvProbe and NetEvent objects for event expressions, and it was making
more then were needed. I've done some merging, though I have some more
things I can do on this front. I'll be working on it for the next snapshot.

I found a whole bunch of bugs with parsing expression lists, for example
module port expressions. The result is actually a smaller parser:-) So
module port expressions should be parsed and elaborated correctly, now.

In the vvm code generator, I've found some room to optimize the generated
code. I detect duplicate initialization of a nexus, and prevent the
excess code being generating. In one slightly degenerate example sent to
me, this change reduced the generated C++ by more then 6 times. I was
pretty amazed.

I've also slightly optimized the special case of behavioral assignments
from simple signal expressions. This removed a few lines of generated
code per assignment. This sort of thing helps compile time performance.

Icarus Verilog 20000512 Snapshot
This is mostly a bug fix snapshot. No new features here, but I'm starting
to buff it up shiny for an upcoming 0.3 release. It looks like I'll be
starting to do release candidates soon, so test this snapshot hard, folks!


I re-implemented flip-flop and RAM synthesis, the new technique should
allow me to make much more complete synthesis. It's still not the nifty
full-scale synthesis I hope to do some day, but it should catch some of
the bigger synthesis problems.

I've also added to XNF synthesis the ability to detect start-up initial
values for flip-flip devices. This causes it to generate INIT= properties
for the devices as appropriate.

I've improved the VVM code generated by the t-vvm code generator. I've
managed to reduce the size of the code generated for some larger models
by 30%, and I should have improved run-time performance in the process.
This should help.

I've also found (thanks to bug reports) and fixed some module port issues.
I bet you can't dream up legal port binding that Icarus Verilog can't
handle:-) This issue should be taken care of.

VPI now includes the ability to set registers. I needed this to implement
a PNG image I/O module. I'm still working on that, I'll distribute it
separately when it is in better shape.

Various other bug fixes in iverilog and elsewhere. Several bug fixes
in the VVM runtime, including some support for the % operator.

I've done some updates to documentation to reflect some of the changes
since 0.2, so you can take a look at that too.

Revision 1.5 / (download) - annotate - [select for diffs], Thu May 11 01:33:49 2000 UTC (23 years ago) by dmcmahill
Branch: MAIN
Changes since 1.4: +3 -3 lines
Diff to previous 1.4 (colored)

update to 20000506 snapshot.

changes from the last packaged snapshot (from the authors announcement):

---------------Icarus Verilog 20000506 Snapshot------------------
A lot of internal reworking has been done on this, so there might be
problems with things like symbol binding. But I think this is much better
then the last snapshot. I am once again starting to think about a
stable release. I'll shoot for the end of May, so if there is anything
you want to see in that release, start pestering me.

The big job has been a rewrite of the symbol table that holds signals.
The previous elaboration and lookup code for signals/memories did not
work properly when hierarchical names were used in the context of tasks
and functions. Also, the old table kept all the signals is a single
lookup table that failed to take advantage of knowledge of the current

All that is changed. signals are now elaborated after parameters and
before processes, so all hierarchical accesses should work properly now,
no matter how contorted. I've also fixed some bugs with function/task
parameter passing.

I've also added some infrastructure for supporting system functions, and
I've added an implementation of the $random system function. This currently
uses the native random(3) C library function, but once I get access to the
standardized algorithm, I'll implement that.

There are also a few fixes to elaboration of ternary operators. They were
a bit touchy about result bit widths.

A few preprocessor bugs have been fixed, especially related to the
`ifdef/`endif tokens. People are all the sudden starting to use the
Icarus Verilog preprocessor, so some long-standing bugs have been caught.

The iverilog command had a few path problems fixed, and the remaining
necessary switches have been added. I really encourage people to start
using iverilog in place of verilog. The test suite now uses iverilog to
run the compiler, so should you. There is a man page.

Revision 1.4 / (download) - annotate - [select for diffs], Sun Apr 30 18:15:17 2000 UTC (23 years, 1 month ago) by dmcmahill
Branch: MAIN
Changes since 1.3: +3 -3 lines
Diff to previous 1.3 (colored)

Update to verilog-current to the 20000428 snapshot.

The many bug fixes and changes since the last packaged snapshot
are (from the authors announcements):

Icarus Verilog 20000428 Snapshot
This one clears up some pretty nasty and subtle bugs. If you've been
sending me bug reports, you're probably turning blue holding your breath
in anticipation of this snapshot. Breath in, Breath out.

Hooray, both force and release work properly. I'm happy about that,
release worked out a bit easier then I expected. These should be useful
to test bench designers.

The big news this past week, however, has been bug fixes. Lots of bug
fixes. I got lots of bug reports and I killed pretty nearly all of
them. There were lots of nasty icky problems with passing parameters
to/from tasks, especially when memory words were involved. I fixed up
a whole bunch of these, and now parameter passing should work pretty
will, modulus the few remaining bugs I'm not seeing yet.

The iverilog command is in better shape now, and I encourage people
to use it in place of the older "verilog" driver script. There is a
man page for iverilog, and it supports all the switches needed to do
simulation and synthesis. I would like people to start getting this
driver well tested and the bugs worked out, because it is going to be
the main driver come the next stable release.

Some neat new XNF features are happening. I synthesize identity compare
in XNF, and a few other missing operators. But the really neato part is
that I've taught Icarus Verilog to generate PIN records for module
ports, so that you can make XNF macros out of Verilog source. If you
elaborate a module that has ports, the XNF code generator will automatically
generate the necessary symbols so that external XNF tools can link the
generated output into larger designs. I've compared the XNF files from
Icarus Verilog with those generated by Abel, and they appear the same
to my eyes.

Icarus Verilog 20000421 Snapshot
Bunches of bug fixes, and a few new features come with this snapshot.
This snapshot makes headway in both simulation and synthesis. I'm
also starting to make a big dent in my todo list for the 0.3 release.

The bunches of little bug fixes in this snapshot are a direct result of
bunches of bug reports this past week that I was able to deal with. If
you've been reporting bugs, this may contain your fix.

I redesigned the process implementation in the vvm backend, so the generated
code is a bit cleaner, and threads are lighter weight. And while I was at
it, fork/join now should work properly. I know there were a bunch of you
out there asking for this, so here it is.

I've incorporated into this release improved runtime support for integer
multiplication, it should now work now matter how incredibly enormous
you make the operands. Thanks to Chris Lattner for contributing the generic

I've improved synthesis somewhat, there were some expressions in some
contexts that were not getting synthesized by the -Fsynth functor. This
is fixed, and I'm also starting to add some XNF specific optimizations
into the -Fxnfio functor. I do sensible things with identity compare,
for example.

I've added the program ``iverilog'' to be a new driver program written
in C instead of as a shell script. This driver supports the -tnull,
-txnf and -tvvm targets, as well as the -E flag that causes only the
preprocessor to be run. This should be interesting to those of you who
are looking for a working preprocessor. I'm still working on the -D and
the -I flags, but I expect this program to replace the script
before the 0.3 release.

Icarus Verilog 20000414 Snapshot
All event handling is now complete. Yet another subject is behind me, and
on I go. By complete, I mean that named events, edge triggers, wait, and
lists of events all work. This took a little longer then I expected, so
some of the other things I wanted to work on had to wait.

As a side effect of event and thread scheduling work, I changed the way
that threads are generated in vvm. The result is that threads should be
a little faster at run time, and a lot faster at compile time. A *LOT*
faster at compile time. (Apparently, Verilog XL is still considerably
faster, but hey, I'm working on it.)

Revision 1.3 / (download) - annotate - [select for diffs], Sun Apr 9 23:11:49 2000 UTC (23 years, 1 month ago) by dmcmahill
Branch: MAIN
Changes since 1.2: +3 -3 lines
Diff to previous 1.2 (colored)

update to verilog-current-20000409.

changes since the last packaged snapshot include:

Icarus Verilog 20000326 Snapshot:
The VVM backend rewrite continues. More templates are gone, and the
bit functions have been pretty much rewritten. The vvm library now handles
bit values with strengths, and most of the devices to the right things
with those strengths.

The most obvious implication of this is that you can write multiple
drivers to a net and expect the values to be properly resolved, and in
particular the HiZ value works as it should. So I am well on the way to
completing strength modeling support.

What is still missing is support for strength specifications in the
Verilog source. Although the parser supports the strength related keywords,
they are not passed on to elaboration, or used to generate drivers with
the proper strengths. So that's in the works.

While doing all this VVM rewrite, I've made the generated code considerably
smaller. And of course fewer templates are used. The upshot of this is that
compiles of larger designs should go a whole lot faster. This is important
because people are using Icarus Verilog for increasingly larger designs.
On some larger examples, I've achieved more then 3X compile time improvement.

Icarus Verilog 20000409 Snapshot:
Named events now work!  Event object declarations and trigger statements
are fully supported, and blocking on a single event also works. I'm not
up to named events in event lists because I'm in the midst of redesigning
the way events on nets and regs are implemented. However, the common case
works fine, so there you are.

I've also added support for some more arithmetic operators. Division and
Modulus now work in many contexts, and are not far from working everywhere.
Also, comparison operators work in places they used to not.

There was a compile error in memory objects that managed to slip through
a couple snapshots, that I finally cured. The problem was pretty gross,
but somehow not quite tickled by my tests. Oh well.

I've integrated some VCD improvements from Anthony Bybell. Some of you
recognize the name as the author of GTKWave, so if he says VCD works like
so, then that's how VCD works:-) Anyhow, he fixed the VCD output to be
more portable, and also a bit smaller when vectors are involved. He also
fixed some bugs with multiple calls to $dumpvars.

Revision 1.2 / (download) - annotate - [select for diffs], Sat Mar 25 21:09:16 2000 UTC (23 years, 2 months ago) by dmcmahill
Branch: MAIN
Changes since 1.1: +5 -4 lines
Diff to previous 1.1 (colored)

Update to verilog-current-20000318.

Notable changes since the last pkg are (from the snapshot announcement):

Parameters are complete.
What this means is that I finally got around to supporting defparam,
and while I was at it I rewrote the entire parameter handling and added
the parameter support included in 1364-2000.

I have rewritten major portions of the VVM backend. The vvm_nexus class
has been introduced to the fray, and all the device implementations in
the VVM library now use the nexus to drive and receive values. An advantage
of this scheme is that the t-vvm backend code (in ivl proper) is simpler,
and so is the generated C++ code.

I also removed most of the template classes. This proved to be a huge
compile-time benefit (though compiling twice as fast really only matters
for large programs) and it doesn't seem likely to hurt run-time performance.
A few remain, either because they seemed harmless (the N-wide logic gates)
or I couldn't yet figure out a good way to replace them (vvm_bitset_t).

A side benefit of this is that the vvm library may now be a modeling
library that ordinary humans can use to write their models in C++. This
may provide the unexpected benefit of heading me towards incremental
compilation of designs. So who was it who was beating me over the head
asking for that?-)

I also fixed a few minor problems with the preprocessor. Those of you
who reported problems with `includes and `defines should check this out.

Revision 1.1 / (download) - annotate - [select for diffs], Tue Mar 7 16:09:15 2000 UTC (23 years, 2 months ago) by dmcmahill
Branch: MAIN

Initial revision

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