[BACK]Return to DESCR CVS log [TXT][DIR] Up to [cvs.NetBSD.org] / pkgsrc / cad / verilog-current

Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.

Diff for /pkgsrc/cad/verilog-current/Attic/DESCR between version 1.3 and 1.4

version 1.3, 2004/01/31 23:36:16 version 1.4, 2005/05/23 08:26:04
Line 4  format. For batch simulation, the compil
Line 4  format. For batch simulation, the compil
 compiled and linked with a run time library (called "vvm") then executed as  compiled and linked with a run time library (called "vvm") then executed as
 a command to run the simulation. For synthesis, the compiler generates  a command to run the simulation. For synthesis, the compiler generates
 netlists in the desired format.  netlists in the desired format.
   
 The compiler proper is intended to parse and elaborate design descriptions  The compiler proper is intended to parse and elaborate design descriptions
 written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and  written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
 complex standard, so it will take some time for it to get there, but that's  complex standard, so it will take some time for it to get there, but that's
Legend:
Removed from v.1.3  
changed lines
  Added in v.1.4
CVSweb <webmaster@jp.NetBSD.org>