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===================================================================
RCS file: /ftp/cvs/cvsroot/pkgsrc/cad/verilog-current/Attic/DESCR,v
rcsdiff: /ftp/cvs/cvsroot/pkgsrc/cad/verilog-current/Attic/DESCR,v: warning: Unknown phrases like `commitid ...;' are present.
retrieving revision 1.3
retrieving revision 1.4
diff -u -p -r1.3 -r1.4
--- pkgsrc/cad/verilog-current/Attic/DESCR	2004/01/31 23:36:16	1.3
+++ pkgsrc/cad/verilog-current/Attic/DESCR	2005/05/23 08:26:04	1.4
@@ -4,7 +4,7 @@ format. For batch simulation, the compil
 compiled and linked with a run time library (called "vvm") then executed as
 a command to run the simulation. For synthesis, the compiler generates
 netlists in the desired format.
-  
+
 The compiler proper is intended to parse and elaborate design descriptions
 written to the IEEE standard IEEE Std 1364-1995. This is a fairly large and
 complex standard, so it will take some time for it to get there, but that's