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Default branch: MAIN
Current tag: MAIN

Revision 1.11 / (download) - annotate - [select for diffs], Thu Dec 27 16:01:54 2018 UTC (13 months, 3 weeks ago) by joerg
Branch: MAIN
CVS Tags: pkgsrc-2019Q4-base, pkgsrc-2019Q4, pkgsrc-2019Q3-base, pkgsrc-2019Q3, pkgsrc-2019Q2-base, pkgsrc-2019Q2, pkgsrc-2019Q1-base, pkgsrc-2019Q1, pkgsrc-2018Q4-base, pkgsrc-2018Q4, HEAD
Changes since 1.10: +3 -1 lines
Diff to previous 1.10 (unified)

async is a keyword for Python 3.7+, so rename it. Bump revision

Revision 1.10 / (download) - annotate - [select for diffs], Thu Apr 12 15:08:58 2018 UTC (22 months, 1 week ago) by mef
Branch: MAIN
CVS Tags: pkgsrc-2018Q3-base, pkgsrc-2018Q3, pkgsrc-2018Q2-base, pkgsrc-2018Q2
Changes since 1.9: +5 -5 lines
Diff to previous 1.9 (unified)

Update cad/MyHDL from 0.9.0 to 0.10

pkgsrc packages altered:
 - cad/MyHDL-gplcver
 - cad/MyHDL-iverilog
 - cad/py-MyHDL

upstream changelog
What new in MyHDL 0.10

The block decorator


The historical approach for hierarchy extraction in MyHDL suffers from
significant issues. This results in complex code, a number of non-intuitive API
concepts, and difficulties for future development.

In this release, a new block decorator is introduced to address these issues.

For an in-depth discussion, see mep-114.


block() :noindex:

    The block decorator enables a method-based API which is more consistent,
    simplifies implementation, and reduces the size of the myhdl namespace.

    The methods work on block instances, created by calling a function
    decorated with the block decorator:

    def myblock(<ports>):
    return <instances>

    inst = myblock(<port-associations>)
    # inst supports the methods of the block instance API

The API on a block instance looks as follows:


    Run a simulation orever(default) or for a specified duration.

<block_instance>.config_sim(backend='myhdl', trace=False)

    - Optional simulation configuration:
    - backend: Defaults to yhdl
    - trace: Enable waveform tracing, default False.


    Quit an active simulation. This is method is currently required because
    only a single simulation can be active.

<block_instance>.convert(hdl='Verilog', **kwargs)

    - Converts MyHDL code to a target HDL.
    - hdl: ϷHDLor Ϸerilog Defaults to Verilog.
    - Supported keyword arguments:
    - path: Destination folder. Defaults to current working dir.
    - name: Module and output file name. Defaults to self.mod.__name__.
    - trace: Whether the testbench should dump all signal waveforms. Defaults to
    - testbench: Verilog only. Specifies whether a testbench should be created.
      Defaults to True.
    - timescale: timescale parameter. Defaults to ns/10ps Verilog only.


    Verify conversion output, by comparing target HDL simulation log with MyHDL
    simulation log.


    Analyze conversion output by compilation with target HDL compiler.

Backwards compatibility issues

In the 0.10 release, the old API still available next to the new API based on
the block decorator.

It is likely that the old API will be deprecated in a future release, resulting
in backwards incompatibility for legacy code. Therefore, users are encouraged
to start using the new API in their development methodology.

Revision 1.9 / (download) - annotate - [select for diffs], Sun Oct 9 03:15:57 2016 UTC (3 years, 4 months ago) by kamil
Branch: MAIN
CVS Tags: pkgsrc-2018Q1-base, pkgsrc-2018Q1, pkgsrc-2017Q4-base, pkgsrc-2017Q4, pkgsrc-2017Q3-base, pkgsrc-2017Q3, pkgsrc-2017Q2-base, pkgsrc-2017Q2, pkgsrc-2017Q1-base, pkgsrc-2017Q1, pkgsrc-2016Q4-base, pkgsrc-2016Q4
Changes since 1.8: +5 -5 lines
Diff to previous 1.8 (unified)

Update MyHDL from 0.8.1 to 0.9.0

pkgsrc packages altered:
 - cad/MyHDL-gplcver
 - cad/MyHDL-iverilog
 - cad/py-MyHDL

pkgsrc changes:
 - Add common Makefile.common for MyHDL packages
 - 0.9.0 supports now Python 3.x
 - update LICENSE to gnu-lgpl-v2.1
 - replace local patch in MyHDL-gplcver and use MAKE_FLAGS to enforce INCS
 - set CC in MyHDL-gplcver
 - setup test target in cad/py-MyHDL
 - share common distinfo
 - switch MASTER_SITES to GitHub

upstream changelog
What new in MyHDL 0.9
Python 3 support

Experimental Python 3 support has been added to MyHDL 0.9. This was a major effort to modernize the code. As a result, Python 2 and 3 are supported from a single codebase.

See Python 3 Support for more info.
Interfaces (Conversion of attribute accesses)

Complex designs often have many signals that are passed to different levels of hierarchy. Typically, many signals logically belong together. This can be modelled by an interface: an object that has a number of Signal objects as its attributes. Grouping signals into an interface simplifies the code, improves efficiency, and reduces errors.

The following is an example of an interface definition:

class Complex:
    def __init__(self, min=-2, max=2):
        self.real = Signal(intbv(0, min=min, max=max))
        self.imag = Signal(intbv(0, min=min, max=max))

Although previous versions supported interfaces for modeling, they were not convertible. MyHDL 0.9 now supports conversion of designs that use interfaces.

The following is an example using the above Complex interface definition:

a,b = Complex(-8,8), Complex(-8,8)
c = Complex(-128,128)

def complex_multiply(clock, reset, a, b, c):

    @always_seq(clock.posedge, reset=reset)
    def cmult(): = (a.real*b.real) - (a.imag*b.imag) = (a.real*b.imag) + (a.imag*b.real)

    return cmult


The proposed solution is to create unique names for attributes which are used by MyHDL generators. The converter will create a unique name by using the name of the parent and the name of the attribute along with the name of the MyHDL module instance. The converter will essentially replace the with an for each interface element. In essence, interfaces are supported using hierarchical name expansion and name mangling.

Note that the MyHDL convertor supports interfaces, even though the target HDLs do not. This is another great example where the convertor supports a high-level feature that is not available in the target HDLs.
See also

For additional information see the original proposal mep-107.
Other noteworthy improvements
ConcatSignal interface

The interface of ConcatSignal was enhanced. In addition to signals, you can now also use constant values in the concatenation.
std_logic type ports

toVHDL() has a new attibute std_logic_ports. When set, only std_logic type ports are used in the interface of the top-level VHDL module.
Development flow

The MyHDL development flow has been modernized by moving to git and github for version control. In addition, travis has set up so that all pull requests are tested automatically, enabling continuous intergration.

The Python 3 support effort was coordinated by Keerthan Jaic, who also implemented most of if. Convertible interfaces were championed by Chris Felton, and implemented by Keerthan Jaic.

MyHDL development is a collaborative effort, as can be seen on github. Thanks to all who contributed with suggestions, issues and pull requests.

Revision 1.8 / (download) - annotate - [select for diffs], Tue Nov 3 00:21:18 2015 UTC (4 years, 3 months ago) by agc
Branch: MAIN
CVS Tags: pkgsrc-2016Q3-base, pkgsrc-2016Q3, pkgsrc-2016Q2-base, pkgsrc-2016Q2, pkgsrc-2016Q1-base, pkgsrc-2016Q1, pkgsrc-2015Q4-base, pkgsrc-2015Q4
Changes since 1.7: +2 -1 lines
Diff to previous 1.7 (unified)

Add SHA512 digests for distfiles for cad category

Problems found with existing distfile for eagle:
No changes made to eagle/distinfo file.

Otherwise, existing SHA1 digests verified and found to be the same on
the machine holding the existing distfiles (morden).  All existing
SHA1 digests retained for now as an audit trail.

Revision 1.7 / (download) - annotate - [select for diffs], Sun Jan 4 02:21:53 2015 UTC (5 years, 1 month ago) by mef
Branch: MAIN
CVS Tags: pkgsrc-2015Q3-base, pkgsrc-2015Q3, pkgsrc-2015Q2-base, pkgsrc-2015Q2, pkgsrc-2015Q1-base, pkgsrc-2015Q1
Changes since 1.6: +4 -4 lines
Diff to previous 1.6 (unified)

 - Add LICENSE= gnu-gpl-v2
 - Update 0.7 to 0.8.1
Release 0.8.1 26-Aug-2014
Maintenance release for 0.8.

Release 0.8 20-May-2013
Full details about new features and changes can be found here:

Revision 1.6 / (download) - annotate - [select for diffs], Wed Apr 13 14:47:18 2011 UTC (8 years, 10 months ago) by drochner
Branch: MAIN
CVS Tags: pkgsrc-2014Q4-base, pkgsrc-2014Q4, pkgsrc-2014Q3-base, pkgsrc-2014Q3, pkgsrc-2014Q2-base, pkgsrc-2014Q2, pkgsrc-2014Q1-base, pkgsrc-2014Q1, pkgsrc-2013Q4-base, pkgsrc-2013Q4, pkgsrc-2013Q3-base, pkgsrc-2013Q3, pkgsrc-2013Q2-base, pkgsrc-2013Q2, pkgsrc-2013Q1-base, pkgsrc-2013Q1, pkgsrc-2012Q4-base, pkgsrc-2012Q4, pkgsrc-2012Q3-base, pkgsrc-2012Q3, pkgsrc-2012Q2-base, pkgsrc-2012Q2, pkgsrc-2012Q1-base, pkgsrc-2012Q1, pkgsrc-2011Q4-base, pkgsrc-2011Q4, pkgsrc-2011Q3-base, pkgsrc-2011Q3, pkgsrc-2011Q2-base, pkgsrc-2011Q2
Changes since 1.5: +4 -4 lines
Diff to previous 1.5 (unified)

update to 0.7
too many changes to list here, see the release notes

Revision 1.5 / (download) - annotate - [select for diffs], Thu May 4 16:58:05 2006 UTC (13 years, 9 months ago) by drochner
Branch: MAIN
CVS Tags: pkgsrc-2011Q1-base, pkgsrc-2011Q1, pkgsrc-2010Q4-base, pkgsrc-2010Q4, pkgsrc-2010Q3-base, pkgsrc-2010Q3, pkgsrc-2010Q2-base, pkgsrc-2010Q2, pkgsrc-2010Q1-base, pkgsrc-2010Q1, pkgsrc-2009Q4-base, pkgsrc-2009Q4, pkgsrc-2009Q3-base, pkgsrc-2009Q3, pkgsrc-2009Q2-base, pkgsrc-2009Q2, pkgsrc-2009Q1-base, pkgsrc-2009Q1, pkgsrc-2008Q4-base, pkgsrc-2008Q4, pkgsrc-2008Q3-base, pkgsrc-2008Q3, pkgsrc-2008Q2-base, pkgsrc-2008Q2, pkgsrc-2008Q1-base, pkgsrc-2008Q1, pkgsrc-2007Q4-base, pkgsrc-2007Q4, pkgsrc-2007Q3-base, pkgsrc-2007Q3, pkgsrc-2007Q2-base, pkgsrc-2007Q2, pkgsrc-2007Q1-base, pkgsrc-2007Q1, pkgsrc-2006Q4-base, pkgsrc-2006Q4, pkgsrc-2006Q3-base, pkgsrc-2006Q3, pkgsrc-2006Q2-base, pkgsrc-2006Q2, cwrapper, cube-native-xorg-base, cube-native-xorg
Changes since 1.4: +4 -4 lines
Diff to previous 1.4 (unified)

update MyHDL to 0.5.1
There is no usable changelog; I've found one real bug closed in the
tracker: A verilog '>>>' is generated as appropriate for signed numbers.

Revision 1.4 / (download) - annotate - [select for diffs], Fri Feb 10 16:06:46 2006 UTC (14 years ago) by drochner
Branch: MAIN
CVS Tags: pkgsrc-2006Q1-base, pkgsrc-2006Q1
Changes since 1.3: +4 -4 lines
Diff to previous 1.3 (unified)

update to 0.5
major changes:
-supports Python decorator syntax for generators (needs 2.4)
-intbv() doesn't have a default anymore
-many improvements to Verilog conversion

Revision 1.3 / (download) - annotate - [select for diffs], Wed Feb 23 14:59:25 2005 UTC (15 years ago) by agc
Branch: MAIN
CVS Tags: pkgsrc-2005Q4-base, pkgsrc-2005Q4, pkgsrc-2005Q3-base, pkgsrc-2005Q3, pkgsrc-2005Q2-base, pkgsrc-2005Q2, pkgsrc-2005Q1-base, pkgsrc-2005Q1
Changes since 1.2: +2 -1 lines
Diff to previous 1.2 (unified)

Add RMD160 digests in addition to SHA1 ones.

Revision 1.2 / (download) - annotate - [select for diffs], Wed Jan 5 15:20:10 2005 UTC (15 years, 1 month ago) by drochner
Branch: MAIN
Changes since 1.1: +3 -3 lines
Diff to previous 1.1 (unified)

update to 0.4.1
* VCD output for waveform viewing
- function additions
- needs Python 2.3, 2.4 is OK
* Conversion to Verilog to provide a path to implementation
* Added cosimulation support for the cver Verilog simulator.
- bugfixes

Revision 1.1 / (download) - annotate - [select for diffs], Thu Jun 5 18:50:54 2003 UTC (16 years, 8 months ago) by drochner
Branch: MAIN

Initial revision

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