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CVS log for pkgsrc/cad/iverilog/buildlink3.mk

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Default branch: MAIN


Revision 1.2 / (download) - annotate - [select for diffs], Sun Jan 7 13:03:56 2018 UTC (6 years, 1 month ago) by rillig
Branch: MAIN
CVS Tags: pkgsrc-2023Q4-base, pkgsrc-2023Q4, pkgsrc-2023Q3-base, pkgsrc-2023Q3, pkgsrc-2023Q2-base, pkgsrc-2023Q2, pkgsrc-2023Q1-base, pkgsrc-2023Q1, pkgsrc-2022Q4-base, pkgsrc-2022Q4, pkgsrc-2022Q3-base, pkgsrc-2022Q3, pkgsrc-2022Q2-base, pkgsrc-2022Q2, pkgsrc-2022Q1-base, pkgsrc-2022Q1, pkgsrc-2021Q4-base, pkgsrc-2021Q4, pkgsrc-2021Q3-base, pkgsrc-2021Q3, pkgsrc-2021Q2-base, pkgsrc-2021Q2, pkgsrc-2021Q1-base, pkgsrc-2021Q1, pkgsrc-2020Q4-base, pkgsrc-2020Q4, pkgsrc-2020Q3-base, pkgsrc-2020Q3, pkgsrc-2020Q2-base, pkgsrc-2020Q2, pkgsrc-2020Q1-base, pkgsrc-2020Q1, pkgsrc-2019Q4-base, pkgsrc-2019Q4, pkgsrc-2019Q3-base, pkgsrc-2019Q3, pkgsrc-2019Q2-base, pkgsrc-2019Q2, pkgsrc-2019Q1-base, pkgsrc-2019Q1, pkgsrc-2018Q4-base, pkgsrc-2018Q4, pkgsrc-2018Q3-base, pkgsrc-2018Q3, pkgsrc-2018Q2-base, pkgsrc-2018Q2, pkgsrc-2018Q1-base, pkgsrc-2018Q1, HEAD
Changes since 1.1: +2 -2 lines
Diff to previous 1.1 (colored)

Fix indentation in buildlink3.mk files.

The actual fix as been done by "pkglint -F */*/buildlink3.mk", and was
reviewed manually.

There are some .include lines that still are indented with zero spaces
although the surrounding .if is indented. This is existing practice.

Revision 1.1 / (download) - annotate - [select for diffs], Sat Oct 8 23:01:45 2016 UTC (7 years, 4 months ago) by kamil
Branch: MAIN
CVS Tags: pkgsrc-2017Q4-base, pkgsrc-2017Q4, pkgsrc-2017Q3-base, pkgsrc-2017Q3, pkgsrc-2017Q2-base, pkgsrc-2017Q2, pkgsrc-2017Q1-base, pkgsrc-2017Q1, pkgsrc-2016Q4-base, pkgsrc-2016Q4

Import iverilog (Icarus Verilog) 10.1.1 as cad/iverilog

It's a rename of cad/verilog to a better name.

Updated DESCR for new package:

Icarus Verilog is intended to compile ALL of the Verilog HDL as described in
the IEEE-1364 standard. Of course, it's not quite there yet. It does currently
handle a mix of structural and behavioral constructs.

Icarus Verilog is not aimed at being a simulator in the traditional sense, but
a compiler that generates code employed by back-end tools.

No objections to rename from <gdt>

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