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Default branch: MAIN
Current tag: pkgsrc-2005Q3-base
Revision 1.4 / (download) - annotate - [select for diffs], Sat Feb 14 17:18:36 2004 UTC (20 years, 2 months ago) by dmcmahill
Branch: MAIN
CVS Tags: pkgsrc-2006Q2-base,
pkgsrc-2006Q2,
pkgsrc-2006Q1-base,
pkgsrc-2006Q1,
pkgsrc-2005Q4-base,
pkgsrc-2005Q4,
pkgsrc-2005Q3-base,
pkgsrc-2005Q3,
pkgsrc-2005Q2-base,
pkgsrc-2005Q2,
pkgsrc-2005Q1-base,
pkgsrc-2005Q1,
pkgsrc-2004Q4-base,
pkgsrc-2004Q4,
pkgsrc-2004Q3-base,
pkgsrc-2004Q3,
pkgsrc-2004Q2-base,
pkgsrc-2004Q2,
pkgsrc-2004Q1-base,
pkgsrc-2004Q1
Changes since 1.3: +116 -186
lines
Diff to previous 1.3 (colored)
update to gnucap-0.34. While here bl3ify. Gnucap 0.34 release notes (02/01/2004) This is a bug fix and compatibility release. 1. Fix bug causing incorrect interpolation of backwards tables. 2. Fix tanh overflow bug. 3. Fix some parsing bugs. 4. Fix occasional "double load" bug. 5. Fix AC sweep with one point. 6. Transient start time really works. 7. Fix occasional assert fail after option short is changed. 8. Fix memory leak resulting from failure to delete unused common. 9. Fix a Z probe bug that sometimes gave wrong answers. 10. Fix a limiting bug that sometimes caused non-convergence. 11. Configure handles isnan. 12. Improvements to logic initialization. It is still not correct. Some things that are still partially implemented: 1. BSIM models, charge effects, "alpha0" parameter. (computed then ignored) 2. Configure still doesn't handle everything. 3. The model compiler still requires too much raw coding. 4. Named nodes. If you set the option "namednodes", it will support named nodes, but some things don't work, so it is off by default. 5. The preliminary IBIS code is now included. For now, it is a standalone executable, that reads an IBIS file and generates a netlist. The netlist requires some editing to use, and is not fully compatible anyway. It is included in hopes of recruiting help in finishing the project. Bugs (nothing new, but needs repeating): 1. The transmission line initial conditions are not propagated until the transient analysis runs. 2. An occasional bogus calculation in MOSFETS occurs when a device is reversed. This sometimes causes nonconvergence. 3. Initialization is strange when repeating an analysis without an intermediate edit. Hot items for a future release (no promises, but highly probable): 1. Verilog-AMS and VHDL-AMS support.