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Default branch: MAIN
Revision 1.4, Sun Oct 9 03:15:57 2016 UTC (5 years, 10 months ago) by kamil
CVS Tags: HEAD
Changes since 1.3: +1 -1 lines
Update MyHDL from 0.8.1 to 0.9.0 pkgsrc packages altered: - cad/MyHDL-gplcver - cad/MyHDL-iverilog - cad/py-MyHDL pkgsrc changes: - Add common Makefile.common for MyHDL packages - 0.9.0 supports now Python 3.x - update LICENSE to gnu-lgpl-v2.1 - replace local patch in MyHDL-gplcver and use MAKE_FLAGS to enforce INCS - set CC in MyHDL-gplcver - setup test target in cad/py-MyHDL - share common distinfo - replace AUTO_MKDIRS with INSTALLATION_DIRS - switch MASTER_SITES to GitHub upstream changelog ================== WhatãàÑÔ new in MyHDL 0.9 Python 3 support Experimental Python 3 support has been added to MyHDL 0.9. This was a major effort to modernize the code. As a result, Python 2 and 3 are supported from a single codebase. See Python 3 Support for more info. Interfaces (Conversion of attribute accesses) Rationale Complex designs often have many signals that are passed to different levels of hierarchy. Typically, many signals logically belong together. This can be modelled by an interface: an object that has a number of Signal objects as its attributes. Grouping signals into an interface simplifies the code, improves efficiency, and reduces errors. The following is an example of an interface definition: class Complex: def __init__(self, min=-2, max=2): self.real = Signal(intbv(0, min=min, max=max)) self.imag = Signal(intbv(0, min=min, max=max)) Although previous versions supported interfaces for modeling, they were not convertible. MyHDL 0.9 now supports conversion of designs that use interfaces. The following is an example using the above Complex interface definition: a,b = Complex(-8,8), Complex(-8,8) c = Complex(-128,128) def complex_multiply(clock, reset, a, b, c): @always_seq(clock.posedge, reset=reset) def cmult(): c.real.next = (a.real*b.real) - (a.imag*b.imag) c.imag.next = (a.real*b.imag) + (a.imag*b.real) return cmult Solution The proposed solution is to create unique names for attributes which are used by MyHDL generators. The converter will create a unique name by using the name of the parent and the name of the attribute along with the name of the MyHDL module instance. The converter will essentially replace the ãàãàwith an ãà×Àãàfor each interface element. In essence, interfaces are supported using hierarchical name expansion and name mangling. Note that the MyHDL convertor supports interfaces, even though the target HDLs do not. This is another great example where the convertor supports a high-level feature that is not available in the target HDLs. See also For additional information see the original proposal mep-107. Other noteworthy improvements ConcatSignal interface The interface of ConcatSignal was enhanced. In addition to signals, you can now also use constant values in the concatenation. std_logic type ports toVHDL() has a new attibute std_logic_ports. When set, only std_logic type ports are used in the interface of the top-level VHDL module. Development flow The MyHDL development flow has been modernized by moving to git and github for version control. In addition, travis has set up so that all pull requests are tested automatically, enabling continuous intergration. Acknowledgments The Python 3 support effort was coordinated by Keerthan Jaic, who also implemented most of if. Convertible interfaces were championed by Chris Felton, and implemented by Keerthan Jaic. MyHDL development is a collaborative effort, as can be seen on github. Thanks to all who contributed with suggestions, issues and pull requests.
Revision 1.3 / (download) - annotate - [select for diffs], Wed Apr 13 16:14:10 2011 UTC (11 years, 4 months ago) by drochner
CVS Tags: pkgsrc-2016Q3-base, pkgsrc-2016Q3, pkgsrc-2016Q2-base, pkgsrc-2016Q2, pkgsrc-2016Q1-base, pkgsrc-2016Q1, pkgsrc-2015Q4-base, pkgsrc-2015Q4, pkgsrc-2015Q3-base, pkgsrc-2015Q3, pkgsrc-2015Q2-base, pkgsrc-2015Q2, pkgsrc-2015Q1-base, pkgsrc-2015Q1, pkgsrc-2014Q4-base, pkgsrc-2014Q4, pkgsrc-2014Q3-base, pkgsrc-2014Q3, pkgsrc-2014Q2-base, pkgsrc-2014Q2, pkgsrc-2014Q1-base, pkgsrc-2014Q1, pkgsrc-2013Q4-base, pkgsrc-2013Q4, pkgsrc-2013Q3-base, pkgsrc-2013Q3, pkgsrc-2013Q2-base, pkgsrc-2013Q2, pkgsrc-2013Q1-base, pkgsrc-2013Q1, pkgsrc-2012Q4-base, pkgsrc-2012Q4, pkgsrc-2012Q3-base, pkgsrc-2012Q3, pkgsrc-2012Q2-base, pkgsrc-2012Q2, pkgsrc-2012Q1-base, pkgsrc-2012Q1, pkgsrc-2011Q4-base, pkgsrc-2011Q4, pkgsrc-2011Q3-base, pkgsrc-2011Q3, pkgsrc-2011Q2-base, pkgsrc-2011Q2
Changes since 1.2: +4 -4 lines
Diff to previous 1.2 (colored)
sync w/ base pkg
Revision 1.2 / (download) - annotate - [select for diffs], Thu May 4 16:58:05 2006 UTC (16 years, 3 months ago) by drochner
CVS Tags: pkgsrc-2011Q1-base, pkgsrc-2011Q1, pkgsrc-2010Q4-base, pkgsrc-2010Q4, pkgsrc-2010Q3-base, pkgsrc-2010Q3, pkgsrc-2010Q2-base, pkgsrc-2010Q2, pkgsrc-2010Q1-base, pkgsrc-2010Q1, pkgsrc-2009Q4-base, pkgsrc-2009Q4, pkgsrc-2009Q3-base, pkgsrc-2009Q3, pkgsrc-2009Q2-base, pkgsrc-2009Q2, pkgsrc-2009Q1-base, pkgsrc-2009Q1, pkgsrc-2008Q4-base, pkgsrc-2008Q4, pkgsrc-2008Q3-base, pkgsrc-2008Q3, pkgsrc-2008Q2-base, pkgsrc-2008Q2, pkgsrc-2008Q1-base, pkgsrc-2008Q1, pkgsrc-2007Q4-base, pkgsrc-2007Q4, pkgsrc-2007Q3-base, pkgsrc-2007Q3, pkgsrc-2007Q2-base, pkgsrc-2007Q2, pkgsrc-2007Q1-base, pkgsrc-2007Q1, pkgsrc-2006Q4-base, pkgsrc-2006Q4, pkgsrc-2006Q3-base, pkgsrc-2006Q3, pkgsrc-2006Q2-base, pkgsrc-2006Q2, cwrapper, cube-native-xorg-base, cube-native-xorg
Changes since 1.1: +2 -2 lines
Diff to previous 1.1 (colored)
update MyHDL to 0.5.1 There is no usable changelog; I've found one real bug closed in the tracker: A verilog '>>>' is generated as appropriate for signed numbers.
Revision 188.8.131.52 / (download) - annotate - [select for diffs] (vendor branch), Fri Feb 10 16:40:02 2006 UTC (16 years, 6 months ago) by drochner
CVS Tags: pkgsrc-base, pkgsrc-2006Q1-base, pkgsrc-2006Q1
Changes since 1.1: +0 -0 lines
Diff to previous 1.1 (colored)
import MyHDL-gplcver-0.5, a GPL Cver vpi module to support cosimulation from py-MyHDL
Revision 1.1 / (download) - annotate - [select for diffs], Fri Feb 10 16:40:02 2006 UTC (16 years, 6 months ago) by drochner
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